Patents by Inventor Stephen W. Bedell
Stephen W. Bedell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11581472Abstract: A gated Josephson junction includes a substrate and a vertical Josephson junction formed on the substrate and extending substantially normal the substrate. The vertical Josephson junction includes a first superconducting layer, a semiconducting layer, and a second superconducting layer. The first superconducting layer, the semiconducting layer, and the second superconducting layer form a stack that is substantially perpendicular to the substrate. The gated Josephson junction includes a gate dielectric layer in contact with the first superconducting layer, the semiconducting layer, and the second superconducting layer at opposing side surfaces of the vertical Josephson junction, and a gate electrically conducting layer in contact with the gate dielectric layer. The gate electrically conducting layer is separated from the vertical Josephson junction by the gate dielectric layer.Type: GrantFiled: August 7, 2019Date of Patent: February 14, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Devendra K. Sadana, Ning Li, Stephen W. Bedell, Sean Hart, Patryk Gumann
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Patent number: 11547440Abstract: An access system having a communication component that interfaces with a first device and a second device, where the first device is located inside or on an entity and coupled to a biological organism of the entity, and where the second device is located outside the entity and a controller component that controls a function of the first device, employing the communication component, to provide treatment to the biological organism of the entity coupled to the first device based on a request received from the second device.Type: GrantFiled: November 26, 2018Date of Patent: January 10, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Steven J. Holmes, Bruce B. Doris, Devendra K. Sadana, Stephen W. Bedell, Jia Chen, Hariklia Deligianni
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Patent number: 11515460Abstract: A quantum computing device is fabricated by forming, on a superconductor layer, a first resist pattern defining a device region and a sensing region within the device region. The superconductor layer within the sensing region is removed, exposing a region of an underlying semiconductor layer outside the device region. The exposed region of the semiconductor layer is implanted, forming an isolation region surrounding the device region. Using an etching process subsequent to the implanting, the sensing region and a portion of the device region of the superconductor layer adjacent to the isolation region are exposed. By depositing a first metal layer within the sensing region, a tunnel junction gate is formed. A reflectrometry wire comprising a second metal within the reflectrometry region is formed. A nanorod contact using the second metal within the portion of the device region outside the sensing region is formed.Type: GrantFiled: November 11, 2019Date of Patent: November 29, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Steven J. Holmes, Devendra K. Sadana, Sean Hart, Ning Li, Stephen W. Bedell, Patryk Gumann
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Patent number: 11482573Abstract: A photovoltaic device including a photovoltaic cell and method of use is disclosed. The photovoltaic cell includes at least a first photovoltaic layer and a second photovoltaic layer arranged in a stack. The first photovoltaic layer has a first thickness and receives light at its top surface. A second photovoltaic layer has a second thickness and is disposed beneath the first photovoltaic layer and receives light passing through the first photovoltaic layer. The first thickness and the second thickness are selected so that a first light absorption at the first photovoltaic layer is equal to a second light absorption at the second photovoltaic layer. The photovoltaic cell is irradiated at its top surface with monochromatic light to generate a current.Type: GrantFiled: November 15, 2017Date of Patent: October 25, 2022Assignee: International Business Machines CorporationInventors: Stephen W. Bedell, Ning Li, Qinglong Li, Kunal Mukherjee, Devendra Sadana, Ghavam G. Shahidi
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Publication number: 20220238663Abstract: Devices, systems, methods, computer-implemented methods, apparatus, and/or computer program products that can facilitate a suspended Majorana fermion device comprising an ion implant defined nanorod in a semiconducting device are provided. According to an embodiment, a quantum computing device can comprise a Majorana fermion device coupled to an ion implanted region. The quantum computing device can further comprise an encapsulation film coupled to the ion implanted region and a substrate layer. The encapsulation film suspends the Majorana fermion device in the quantum computing device.Type: ApplicationFiled: April 18, 2022Publication date: July 28, 2022Inventors: Steven J. Holmes, Devendra K. Sadana, Sean Hart, Patryk Gumann, Stephen W. Bedell, Ning Li
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Patent number: 11316022Abstract: Devices, systems, methods, computer-implemented methods, apparatus, and/or computer program products that can facilitate a suspended Majorana fermion device comprising an ion implant defined nanorod in a semiconducting device are provided. According to an embodiment, a quantum computing device can comprise a Majorana fermion device coupled to an ion implanted region. The quantum computing device can further comprise an encapsulation film coupled to the ion implanted region and a substrate layer. The encapsulation film suspends the Majorana fermion device in the quantum computing device.Type: GrantFiled: November 19, 2019Date of Patent: April 26, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Steven J. Holmes, Devendra K. Sadana, Sean Hart, Patryk Gumann, Stephen W. Bedell, Ning Li
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Patent number: 11302857Abstract: A method for fabricating an active cooling structure, comprising forming an array of Superconductor-Insulator-Normal Metal (NIS) tunnel structures between a non-conducting layer and a superconducting layer. The non-superconducting layer may comprise a plurality of non-superconducting traces running in a first direction. The superconductor layer may comprise a plurality of superconducting traces running in a second direction.Type: GrantFiled: November 19, 2019Date of Patent: April 12, 2022Assignee: International Business Machines CorporationInventors: Steven J. Holmes, Devendra K. Sadana, Stephen W. Bedell, Ning Li
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Patent number: 11239150Abstract: A tetherless system-in-package includes a first integrated circuit (IC) chip having interconnects and energy harvesting elements. A super-capacitor is configured to store a charge output by the energy harvesting elements. At least a second IC chipset including a smart chip and an optical I/O or an RF I/O is aligned and bonded to at least one of the interconnects of the first IC chip. The first IC chip and the second IC chip are configured to receive a portion of the charge stored by the super-capacitor.Type: GrantFiled: March 25, 2020Date of Patent: February 1, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Frank Robert Libsch, Stephen W. Bedell, Ning Li
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Patent number: 11217717Abstract: A method of forming a photovoltaic device that includes ion implanting a first conductivity type dopant into first regions of a semiconductor layer of an SOI substrate, wherein the first regions are separated by a first pitch; and ion implanting a second conductivity type dopant into second regions of the semiconductor layer of the SOI substrate. The second regions are separated by a second pitch. Each second conductivity type implanted region of the second regions is in direct contact with first conductivity type implanted region of the first regions to provide a plurality of p-n junctions, and adjacent p-n junctions are separated by an intrinsic portion of the semiconductor layer to provide P-I-N cells that are horizontally oriented.Type: GrantFiled: October 8, 2019Date of Patent: January 4, 2022Assignee: International Business Machines CorporationInventors: Stephen W. Bedell, Ning Li, Devendra K. Sadana, Ghavam G. Shahidi
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Patent number: 11211542Abstract: An active cooling structure, comprising a non-superconducting layer, a superconducting layer, and an array of Superconductor-Insulator-Normal Metal (NIS) tunnel junctions. The non-superconducting layer may comprise a plurality of non-superconducting traces. The superconducting layer may comprise a plurality of superconducting traces. The array of Superconductor-Insulator-Normal Metal (NIS) tunnel junctions may be located between the plurality of non-superconducting traces and the plurality of superconducting traces.Type: GrantFiled: November 19, 2019Date of Patent: December 28, 2021Assignee: International Business Machines CorporationInventors: Steven J. Holmes, Devendra K. Sadana, Stephen W. Bedell, Ning Li
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Publication number: 20210399346Abstract: One or more trenches in a silicon substrate have an electrically active surface at a trench base and metal layer disposed on the electrically active surface. Precursor materials are disposed and/or formed on the metal layer in the trench. An anode is patterned either exclusively in the 3D trench or in the 3D trench, sidewalls and field of the substrate, where the anode patterning transforms and/or moves the precursor materials in the trench into some novel compositions of matter and other final operational structures for the device, e.g. layers of metallic Lithium for energy storage and different concentrations of Lithium-silicon species in the substrate. A multi-faceted mechanism is disclosed for Al2O3 silicon interfacial additives. When the anode is patterned both in and outside the 3D wells, Al2O3 provides an for electron-conductive Li-metal interface that enables homogenous plating on both the insulated substrate field as well as active silicon trench base where Al2O3 acts as a barrier to Li—Si diffusion.Type: ApplicationFiled: June 22, 2020Publication date: December 23, 2021Inventors: John Collins, Stephen W. Bedell, John Ott, Devendra K. Sadana
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Patent number: 11195086Abstract: Techniques are disclosed for fabricating and using a neuromorphic computing device including biological neurons. For example, a method for fabricating a neuromorphic computing device includes forming a channel in a first substrate and forming at least one sensor in a second substrate. At least a portion of the channel in the first substrate is seeded with a biological neuron growth material. The second substrate is attached to the first substrate such that the at least one sensor is proximate to the biological neuron growth material and growth of the seeded biological neuron growth material is stimulated to grow a neuron in the at least a portion of the channel.Type: GrantFiled: May 28, 2019Date of Patent: December 7, 2021Assignee: International Business Machines CorporationInventors: Steven J. Holmes, Devendra K. Sadana, Stephen W. Bedell, Teodor K. Todorov
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Patent number: 11195999Abstract: A PCM cell is provided that includes a silver (Ag) doped Ge2Sb2Te5 (GST) alloy layer as the PCM material. The PCM cell containing the Ag doped GST alloy layer exhibits a reduced reset state resistance drift as compared to an equivalent PCM cell in which a non-Ag doped GST alloy layer is used. In some embodiments and depending on the Ag dopant concentration of the Ag doped GST alloy layer, a constant reset state resistance or even a negative reset state resistance drift can be obtained.Type: GrantFiled: November 13, 2019Date of Patent: December 7, 2021Assignee: International Business Machines CorporationInventors: Ning Li, Joel P. de Souza, Stephen W. Bedell, Devendra K. Sadana
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Patent number: 11187672Abstract: A method for making a hydrophobic biosensing device includes forming alternating layers over a top and sides of a fin on a dielectric layer to form a stack of layers. The stack of layers are planarized to expose the top of the fin. The fin and every other layer are removed to form a cathode group of fins and an anode group of fins. A hydrophobic surface on the two groups of fins.Type: GrantFiled: January 3, 2020Date of Patent: November 30, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ali Afzali-Ardakani, Karthik Balakrishnan, Stephen W. Bedell, Pouya Hashemi, Bahman Hekmatshoartabari, Alexander Reznicek
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Patent number: 11174545Abstract: In an embodiment, a fabrication method comprises forming first and second electrodes over a substrate that includes a nanowire that extends between, and beneath portions of, the first and second electrodes. The method also includes forming a mask structure that defines at least one opening over a portion of the nanowire and defines at least one overhang portion over a gap between the substrate and the mask. The method further includes depositing a first gate electrode on the substrate and overlapping a third region of the nanowire, and depositing a second gate electrode on the substrate and overlapping a fourth region of the nanowire. The depositing of the first gate electrode includes depositing conductive material through the at least one opening from a first oblique angle, and the depositing of the second gate electrode includes depositing conductive material through the at least one opening from a second oblique angle.Type: GrantFiled: November 6, 2019Date of Patent: November 16, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Steven J. Holmes, Devendra K. Sadana, Stephen W. Bedell, Ning Li
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Patent number: 11177427Abstract: According to an embodiment of the present invention, a method for fabricating a Majorana fermion structure includes providing a substrate, and depositing a superconducting material on the substrate. The method includes depositing a magnetic material on the superconducting material using angled deposition through a mask. The method includes annealing the magnetic material and the superconducting material to form a magnetic nanowire partially embedded in the superconducting material such that the magnetic nanowire and the superconducting material form a Majorana fermion structure.Type: GrantFiled: February 14, 2020Date of Patent: November 16, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen W. Bedell, Steven J. Holmes, Ning Li, Devendra K. Sadana
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Patent number: 11164992Abstract: A semiconductor device includes a substrate and a buffer layer disposed on a first portion, a second portion, and a third portion of the substrate. The semiconductor device further includes a multilayer light-emitting diode (LED) stack disposed on the first portion of the substrate, and an optical sensor disposed on the second portion of the substrate. The semiconductor device further includes at least one electrode disposed on the third portion of the substrate, a first conductor in contact with the multilayer LED stack, and a second conductor in contact with the optical sensor. The at least one electrode, the first conductor, and the second conductor are formed of a glassy carbon material.Type: GrantFiled: November 13, 2019Date of Patent: November 2, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Steve Holmes, Devendra Sadana, Stephen W. Bedell, Bruce Doris, Hariklia Deligianni, Jia Chen
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Patent number: 11164628Abstract: An apparatus includes an analog phase change memory array, including an array of cells addressable and accessible through first lines and second lines. The apparatus includes device(s) coupled to one or more of the first lines. The device(s) is/are able to be coupled to or decoupled from the one or more first lines to compensate for phase change memory resistance drift in resistance of at least one of the cells in the one or more first lines. The apparatus may also include control circuitry configured to send, using the first lines and second lines, a same set pulse through the device(s) to multiple individual phase change memory resistors in the phase change memory array sequentially once every period.Type: GrantFiled: February 21, 2020Date of Patent: November 2, 2021Assignee: International Business Machines CorporationInventors: Ning Li, Wanki Kim, Stephen W. Bedell, Devendra K. Sadana
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Patent number: 11145580Abstract: An energy storage device for an integrated circuit carrier package. One or more energy storage elements have contact elements arranged thereon that include an anode, a cathode, and an isolated common pad. The energy storage element is configured for arrangement in a stack of energy storage elements in which the isolated common pad is shorted to one of the anode or the cathode by bonded conductive interconnects.Type: GrantFiled: March 25, 2020Date of Patent: October 12, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Frank Robert Libsch, Stephen W. Bedell, Ning Li
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Publication number: 20210305149Abstract: A tetherless system-in-package includes a first integrated circuit (IC) chip having interconnects and energy harvesting elements. A super-capacitor is configured to store a charge output by the energy harvesting elements. At least a second IC chipset including a smart chip and an optical I/O or an RF I/O is aligned and bonded to at least one of the interconnects of the first IC chip. The first IC chip and the second IC chip are configured to receive a portion of the charge stored by the super-capacitor.Type: ApplicationFiled: March 25, 2020Publication date: September 30, 2021Inventors: Frank Robert Libsch, Stephen W. Bedell, Ning Li