Patents by Inventor Steven Howard Voldman

Steven Howard Voldman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6288880
    Abstract: A magneto-resistive read head having a “parasitic shield” provides an alternative path for currents associated with sparkovers, thus preventing such currents from damaging the read head. The parasitic shield is provided in close proximity to a conventional magnetic shield. The electrical potential of parasitic shield is held essentially equal to the electrical potential of the sensor element. If charges accumulate on the conventional shield, current will flow to the parasitic shield at a lower potential than would be required for current to flow between the conventional shield and the sensor element. Alternatively, conductive spark gap devices are electrically coupled to sensor element leads and to each magnetic shield. Each spark gap device is brought within very close proximity of the substrate to provide an alternative path for charge that builds up between the sensor element and the substrate to be discharged.
    Type: Grant
    Filed: November 4, 1999
    Date of Patent: September 11, 2001
    Assignee: International Business Machines Corporation
    Inventors: Timothy Scott Hughbanks, Neil Leslie Robertson, Steven Howard Voldman, Albert John Wallash
  • Patent number: 6281593
    Abstract: A body contact to a SOI device is created by providing a deeper buried oxide region for providing connection to the FET body.
    Type: Grant
    Filed: December 6, 1999
    Date of Patent: August 28, 2001
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey Scott Brown, Andres Bryant, Robert J. Gauthier, Jr., Steven Howard Voldman
  • Publication number: 20010010964
    Abstract: A method of dissipating charge from a substrate of an SOI device is provided wherein a charge dissipation path is formed in the device so that it abuts the various layers thereof. Exemplary charge dissipation paths include high conductive materials, resistive means, and field emission or arc discharge means. SOI structures having said charge dissipation path formed therein are also provided. SOI ESD circuits between SOI substrate and chip ground Vss are provided herein.
    Type: Application
    Filed: April 9, 2001
    Publication date: August 2, 2001
    Applicant: International Business Machines Corporation
    Inventors: Stephen Frank Geissler, Steven Howard Voldman
  • Patent number: 6245600
    Abstract: A method of dissipating charge from a substrate of an SOI device is provided wherein a charge dissipation path is formed in the device so that it abuts the various layers thereof. Exemplary charge dissipation paths include high conductive materials, resistive means, and field emission or arc discharge means. SOI structures having said charge dissipation path formed therein are also provided. SOI ESD circuits between SOI substrate and chip ground Vss are provided herein.
    Type: Grant
    Filed: July 1, 1999
    Date of Patent: June 12, 2001
    Assignee: International Business Machines Corporation
    Inventors: Stephen Frank Geissler, Steven Howard Voldman
  • Patent number: 6229372
    Abstract: An active clamp circuit for digital circuits includes a first MOSFET serially connected between an upper power supply voltage and an input terminal to be clamped, and a second MOSFET serially connected between a lower voltage power supply and the input terminal. The voltages at the gates of the first and second MOSFETs are held at constant first and second reference voltages by a reference circuit and the first reference voltage at the gate of the first MOSFET is less than the second reference voltage at the gate of the second MOSFET. The first and second reference voltages can be changed by connecting the reference circuit to power supply voltages other than the power supply voltages to which the first and second MOSFETs are connected. The reference voltages can also be varied by adding stages of transistors which act as resistors in parallel to the reference circuit. When the first reference voltage is to be varied, it is recommended that the transistors of opposite type be biased independently.
    Type: Grant
    Filed: November 19, 1999
    Date of Patent: May 8, 2001
    Assignee: International Business Machines Corporation
    Inventors: Benjamin William Mashak, Robert Russell Williams, Steven Howard Voldman, David TinSun Hui
  • Patent number: 6144086
    Abstract: A method and structure for improving the latch-up characteristic of semiconductor devices is provided. A dual depth STI is used to isolate the wells from each other. The trench has a first substantially horizontal surface at a first depth and a second substantially horizontal surface at a second depth which is deeper than the first depth. The n- and p-wells are formed on either side of the trench. A highly doped region is formed in the substrate underneath the second substantially horizontal surface of the trench. The highly doped region abuts both the first and the second wells and extends the isolation of the trench.
    Type: Grant
    Filed: April 30, 1999
    Date of Patent: November 7, 2000
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey Scott Brown, Robert J. Gauthier, Jr., Randy William Mann, Steven Howard Voldman
  • Patent number: 6097068
    Abstract: A semiconductor device and method of fabrication for such device in which a P- epitaxial layer is positioned above a P++ substrate. A P++ buried layer implant is positioned within the device between the P++ substrate and the P- epitaxial layer. A connecting p+ implant is placed within the epitaxial layer above the buried p+ blanket layer implant. In one exemplary embodiment, the device includes a shallow P-well with the P+ connecting implant in a position within the epitaxial layer connecting the shallow P-well and the buried P+ blanket implant layer.
    Type: Grant
    Filed: January 22, 1998
    Date of Patent: August 1, 2000
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey Scott Brown, Stephen Scott Furkay, Robert John Gauthier, Jr., Xiaowei Tian, Minh Ho Tong, Steven Howard Voldman
  • Patent number: 6081409
    Abstract: A magneto-resistive read head having a "parasitic shield" provides an alternative path for currents associated with sparkovers, thus preventing such currents from damaging the read head. The parasitic shield is provided in close proximity to a conventional magnetic shield. The electrical potential of parasitic shield is held essentially equal to the electrical potential of the sensor element. If charges accumulate on the conventional shield, current will flow to the parasitic shield at a lower potential than would be required for current to flow between the conventional shield and the sensor element. Alternatively, conductive spark gap devices are electrically coupled to sensor element leads and to each magnetic shield. Each spark gap device is brought within very close proximity of the substrate to provide an alternative path for charge that builds up between the sensor element and the substrate to be discharged.
    Type: Grant
    Filed: October 28, 1997
    Date of Patent: June 27, 2000
    Assignee: International Business Machines Corporation
    Inventors: Timothy Scott Hughbanks, Neil Leslie Robertson, Steven Howard Voldman, Albert John Wallash
  • Patent number: 6074899
    Abstract: Three-dimensional ESD structures are constructed in SOI technology that utilize both bulk devices and thin film SOI devices.
    Type: Grant
    Filed: February 5, 1999
    Date of Patent: June 13, 2000
    Assignee: International Business Machines Corporation
    Inventor: Steven Howard Voldman
  • Patent number: 6057184
    Abstract: A semiconductor device and method of fabrication for such device in which a P- epitaxial layer is positioned above a P++ substrate. A P++ buried layer implant is positioned within the device between the P++ substrate and the P- epitaxial layer. A connecting p+ implant is placed within the epitaxial layer above the buried p+ blanket layer implant. In one exemplary embodiment, the device includes a shallow P-well with the P+ connecting implant in a position within the epitaxial layer connecting the shallow P-well and the buried P+ blanket implant layer.
    Type: Grant
    Filed: March 21, 1997
    Date of Patent: May 2, 2000
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey Scott Brown, Stephen Scott Furkay, Robert John Gauthier, Jr., Xiaowei Tian, Minh Ho Tong, Steven Howard Voldman
  • Patent number: 5945713
    Abstract: On-chip ESD protection for semiconductor chips with mixed-voltage interface applications and internal multiple power bus architecture are described. ESD robustness in shallow trench isolation 0.50- and 0.25-micron channel-length CMOS technologies is presented in the form of ESD structures and circuits including hybrid three-rail and mixed voltage interface embodiments.
    Type: Grant
    Filed: December 12, 1996
    Date of Patent: August 31, 1999
    Assignee: International Business Machines Corporation
    Inventor: Steven Howard Voldman
  • Patent number: 5943254
    Abstract: Multichip semiconductor structures with consolidated circuitry are disclosed, along with programmable electrostatic discharge (ESD) protection circuits for chip input/output (I/O) nodes. The multichip structures include a first semiconductor chip having a first circuit at least partially providing a first predetermined circuit function, and a second semiconductor chip electrically and mechanically coupled to the first semiconductor chip. The second semiconductor device chip has a second circuit that at least partially provides a circuit function to the first circuit of the first semiconductor chip. In one embodiment, the first semiconductor chip includes a memory array chip, while the second semiconductor chip includes a logic chip wherein at least some peripheral circuitry necessary for accessing the memory array of the memory array chip resides within the logic chip. This allows the removal of redundant circuitry from identical chips of a multichip structure.
    Type: Grant
    Filed: August 28, 1997
    Date of Patent: August 24, 1999
    Assignee: International Business Machines Corporation
    Inventors: Paul Evans Bakeman, Jr., Claude Louis Bertin, Erik Leight Hedberg, James Marc Leas, Steven Howard Voldman
  • Patent number: 5930098
    Abstract: Interchip and intrachip electrical discharge suppression connections or networks are disclosed for three-dimensional multichip semiconductor structures. The interchip suppression networks electrically intercouple the power planes of the semiconductor device chips in the structure. This, in combination with conventional intrachip suppression networks present on the external connects or input/output pins of the individual chips in the structure, provides complete power plane-to-power plane, external connect-to-power plane and external connect-to-external connect protection against electrical discharge events, such as an electrostatic discharge occurring during handling and testing of the structure. The interchip electrical discharge suppression networks can be placed on an end layer or end semiconductor chip of the three-dimensional multichip semiconductor structure and connect to individual chips in the structure via an edge surface metallization.
    Type: Grant
    Filed: July 10, 1997
    Date of Patent: July 27, 1999
    Assignee: International Business Machines Corporation
    Inventors: Steven Howard Voldman, Paul Evans Bakeman, Jr.
  • Patent number: 5923067
    Abstract: Three-dimensional ESD structures are constructed in SOI technology that utilize both bulk devices and thin film SOI devices.
    Type: Grant
    Filed: April 4, 1997
    Date of Patent: July 13, 1999
    Assignee: International Business Machines Corporation
    Inventor: Steven Howard Voldman
  • Patent number: 5807791
    Abstract: Multichip semiconductor structures with consolidated circuitry are disclosed, along with programmable electrostatic discharge (ESD) protection circuits for chip input/output (I/O) nodes. The multichip structures include a first semiconductor chip having a first circuit at least partially providing a first predetermined circuit function, and a second semiconductor chip electrically and mechanically coupled to the first semiconductor chip. The second semiconductor device chip has a second circuit that at least partially provides a circuit function to the first circuit of the first semiconductor chip. In one embodiment, the first semiconductor chip comprises a memory array chip, while the second semiconductor chip comprises a logic chip wherein at least some peripheral circuitry necessary for accessing the memory array of the memory array chip resides within the logic chip. This allows the removal of redundant circuitry from identical chips of a multichip structure.
    Type: Grant
    Filed: January 2, 1997
    Date of Patent: September 15, 1998
    Assignee: International Business Machines Corporation
    Inventors: Claude Louis Bertin, Erik Leigh Hedberg, James Marc Leas, Steven Howard Voldman
  • Patent number: 5786237
    Abstract: A fabrication method for manufacturing a monolithic electronic module comprising a plurality of stacked planar extending arrays of integrated circuit chips. The fabrication method includes dicing a wafer of integrated circuit chips into a plurality of arrays of integrated circuit chips. The arrays of integrated circuit chips are then stacked to form an electronic module. A metallization pattern may be deposited on a substantially planar surface of the electronic module, and used to interconnect the various arrays of integrated circuit chips contained therein. Specific details of the fabrication method and resultant multi-chip package are set forth.
    Type: Grant
    Filed: August 16, 1995
    Date of Patent: July 28, 1998
    Assignee: International Business Machines Corporation
    Inventors: Martha Ashley Clark Cockerill, John George Maltabes, Loretta Jean O'Connor, Steven Howard Voldman
  • Patent number: 5771571
    Abstract: A thin film slider with an on-board multi-layer integrated circuit includes a substrate with an air bearing surface and a substantially parallel upper surface spanned by a deposit end. A magnetic head being formed at the deposit end, positioned to magnetically exchange data with a magnetic recording medium that passes beneath the air bearing surface. The upper surface bears an integrated multi-layer accessory circuit, which may be prepared using the CUBE process. Hence, components and vias of the different circuit layers are attached by interconnections that span the edges of the circuit layers. The accessory circuit preferably includes one or more memory devices, such as a cache memory, a DRAM circuit, an EPROM circuit, or another memory circuit appropriate to the application. In embodiments where the magnetic head is a magnetoresistive ("MR") head, the accessory circuit may also include a pre-amplifier and a sensing circuit to support operation of the MR head.
    Type: Grant
    Filed: January 21, 1997
    Date of Patent: June 30, 1998
    Assignee: International Business Machines Corporation
    Inventors: Steven Howard Voldman, Albert John Wallash
  • Patent number: 5761009
    Abstract: A magneto-resistive read head having a "parasitic shield" provides an alternative path for currents associated with sparkovers, thus preventing such currents from damaging the read head. The parasitic shield is provided in close proximity to a conventional magnetic shield. The electrical potential of parasitic shield is held essentially equal to the electrical potential of the sensor element. If charges accumulate on the conventional shield, current will flow to the parasitic shield at a lower potential than would be required for current to flow between the conventional shield and the sensor element. Alternatively, conductive spark gap devices are electrically coupled to sensor element leads and to each magnetic shield. Each spark gap device is brought within very close proximity of the substrate to provide an alternative path for charge that builds up between the sensor element and the substrate to be discharged.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: June 2, 1998
    Assignee: International Business Machines Corporation
    Inventors: Timothy Scott Hughbanks, Neil Leslie Robertson, Steven Howard Voldman, Albert John Wallash
  • Patent number: 5731945
    Abstract: Multichip semiconductor structures with consolidated circuitry are disclosed, along with programmable electrostatic discharge (ESD) protection circuits for chip input/output (I/O) nodes. The multichip structures include a first semiconductor chip having a first circuit at least partially providing a first predetermined circuit function, and a second semiconductor chip electrically and mechanically coupled to the first semiconductor chip. The second semiconductor device chip has a second circuit that at least partially provides a circuit function to the first circuit of the first semiconductor chip. In one embodiment, the first semiconductor chip comprises a memory array chip, while the second semiconductor chip comprises a logic chip wherein at least some peripheral circuitry necessary for accessing the memory array of the memory array chip resides within the logic chip. This allows the removal of redundant circuitry from identical chips of a multichip structure.
    Type: Grant
    Filed: January 2, 1997
    Date of Patent: March 24, 1998
    Assignee: International Business Machines Corporation
    Inventors: Claude Louis Bertin, Erik Leight Hedberg, James Maro Leas, Steven Howard Voldman
  • Patent number: 5731941
    Abstract: An enhanced electrostatic discharge suppression circuit is disclosed for protecting integrated circuit chips from electrostatic discharges or other potentially damaging voltage transients on an input/output pad. The suppression circuit includes a discharge circuit, electrically coupled to the input/output pad, having a diode comprising a diffusion in a substrate well formed in a substrate. The diffusion is connected to the input/output pad of the integrated circuit. A capacitor is locally provided to couple the substrate well to the substrate. The capacitor is sized to maintain the diode in a forward-bias mode during the electrostatic discharge event, thereby facilitating dissipating of the electrostatic discharge. The capacitor comprises a trench capacitor, which depending upon the configuration, may function as a guard ring for the discharge circuit. Certain beneficial parasitic effects are also discussed in association with integration of a trench capacitor into the suppression circuit.
    Type: Grant
    Filed: September 8, 1995
    Date of Patent: March 24, 1998
    Assignee: International Business Machines Corporation
    Inventors: Michael John Hargrove, Steven Howard Voldman