Patents by Inventor Steven M. Shank

Steven M. Shank has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • PIXEL ARRAYS INCLUDING HETEROGENOUS PHOTODIODE TYPES
    Publication number: 20220181361
    Abstract: Structures including multiple photodiodes and methods of fabricating a structure including multiple photodiodes. A substrate has a first trench extending to a first depth into the substrate and a second trench extending to a second depth into the substrate that is greater than the first depth. A first photodiode includes a first light-absorbing layer containing a first material positioned in the first trench. A second photodiode includes a second light-absorbing layer containing a second material positioned in the second trench. The first material and the second material each include germanium.
    Type: Application
    Filed: December 7, 2020
    Publication date: June 9, 2022
    Inventors: John J. Ellis-Monaghan, Steven M. Shank, Rajendran Krishnasamy, Ramsey Hazbun
  • Boolean temperature sensing using phase transition material
    Patent number: 11333558
    Abstract: One device disclosed herein includes, among other things, a substrate, a first resistor comprising a first phase transition material formed above the substrate, the first phase transition material exhibiting a first dielectric phase for temperatures less than a first phase transition temperature and a first semiconductor phase for temperatures greater than the first phase transition temperature, and logic to detect a transition of the first resistor to the first semiconductor phase.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: May 17, 2022
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Vibhor Jain, Anthony K. Stamper, John J. Pekarik, Steven M. Shank
  • Avalanche photodiode
    Patent number: 11322639
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an avalanche photodiode and methods of manufacture. The structure includes: a substrate material having a trench with sidewalls and a bottom composed of the substrate material; a first semiconductor material lining the sidewalls and the bottom of the trench; a photosensitive semiconductor material provided on the first semiconductor material; and a third semiconductor material provided on the photosensitive semiconductor material.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: May 3, 2022
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Mark D. Levy, Siva P. Adusumilli, John J. Ellis-Monaghan, Vibhor Jain, Ramsey Hazbun, Pernell Dongmo, Cameron E. Luce, Steven M. Shank, Rajendran Krishnasamy
  • Bulk wafer switch isolation
    Patent number: 11322387
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bulk wafer switch isolation structures and methods of manufacture. The structure includes: a bulk substrate material; an active region on the bulk substrate material; an inactive region adjacent to the active region; and an amorphous material covering the bulk substrate material in the inactive region, which is adjacent to the active region.
    Type: Grant
    Filed: October 13, 2020
    Date of Patent: May 3, 2022
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Uzma Rana, Anthony K. Stamper, Steven M. Shank, Brett T. Cucci
  • Vertical field effect transistor (FET) with source and drain structures
    Patent number: 11316045
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical field effect transistors (FETS) and methods of manufacture. The structure includes: a substrate material; at least one vertically oriented gate structure extending into the substrate material and composed of a gate dielectric material and conductive gate material; and vertically oriented source/drain regions extending into the substrate material and composed of conductive dopant material and a silicide on the source/drain regions.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: April 26, 2022
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Anthony K. Stamper, Aaron L. Vallett, Steven M. Shank, John J. Ellis-Monaghan
  • Semiconductor structures including stacked depleted and high resistivity regions
    Patent number: 11315825
    Abstract: Structures including electrical isolation and methods associated with forming such structures. A semiconductor layer has a top surface, a polycrystalline region, and a single-crystal region between the polycrystalline region and the top surface. An isolation band is located beneath the single-crystal region. The isolation band contains a first concentration of an n-type dopant and a second concentration of a p-type dopant, and a net difference between the first concentration and the second concentration is within a range of about five percent to about fifteen percent.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: April 26, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Michel J. Abou-Khalil, Aaron Vallett, Steven M. Shank, Bojidha Babu, John J. Ellis-Monaghan, Anthony K. Stamper
  • HETEROJUNCTION BIPOLAR TRANSISTOR WITH BURIED TRAP RICH ISOLATION REGION
    Publication number: 20220122968
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich isolation region and methods of manufacture. The structure includes: a first heterojunction bipolar transistor; a second heterojunction bipolar transistor; and a trap rich isolation region embedded within a substrate underneath both the first heterojunction bipolar transistor and the second heterojunction bipolar transistor.
    Type: Application
    Filed: October 20, 2020
    Publication date: April 21, 2022
    Inventors: Vibhor JAIN, John J. ELLIS-MONAGHAN, Anthony K. STAMPER, Steven M. SHANK, John J. PEKARIK
  • HETEROJUNCTION BIPOLAR TRANSISTOR WITH BURIED TRAP RICH ISOLATION REGION
    Publication number: 20220123107
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich region and methods of manufacture. The structure includes: a trap rich isolation region embedded within the bulk substrate; and a heterojunction bipolar transistor above the trap rich isolation region, with its sub-collector region separated by the trap rich isolation region by a layer of the bulk substrate.
    Type: Application
    Filed: October 20, 2020
    Publication date: April 21, 2022
    Inventors: Vibhor JAIN, Anthony K. STAMPER, John J. ELLIS-MONAGHAN, Steven M. SHANK, Rajendran KRISHNASAMY
  • BULK WAFER SWITCH ISOLATION
    Publication number: 20220115262
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bulk wafer switch isolation structures and methods of manufacture. The structure includes: a bulk substrate material; an active region on the bulk substrate material; an inactive region adjacent to the active region; and an amorphous material covering the bulk substrate material in the inactive region, which is adjacent to the active region.
    Type: Application
    Filed: October 13, 2020
    Publication date: April 14, 2022
    Inventors: Uzma RANA, Anthony K. STAMPER, Steven M. SHANK, Brett T. CUCCI
  • PHOTODIODE WITH INTEGRATED, LIGHT FOCUSING ELEMENT
    Publication number: 20220115549
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a photodiode with an integrated, light focusing elements and methods of manufacture. The structure includes: a trench photodiode comprising a domed structure; and a doped material on the domed structure, the doped material having a concave underside surface.
    Type: Application
    Filed: October 8, 2020
    Publication date: April 14, 2022
    Inventors: Rajendran KRISHNASAMY, Steven M. SHANK, John J. ELLIS-MONAGHAN, Ramsey HAZBUN
  • Field effect transistors with back gate contact and buried high resistivity layer
    Patent number: 11296190
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors with back gate contact and buried high resistivity layer and methods of manufacture. The structure includes: a handle wafer comprising a single crystalline semiconductor region; an insulator layer over the single crystalline semiconductor region; a semiconductor layer over the insulator layer; a high resistivity layer in the handle wafer, separated from the insulator layer by the single crystalline semiconductor region; and a device on the semiconductor layer.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: April 5, 2022
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Vibhor Jain, Anthony K. Stamper, Steven M. Shank, John J. Ellis-Monaghan, John J. Pekarik
  • STRUCTURE INCLUDING POLYCRYSTALLINE RESISTOR WITH DOPANT-INCLUDING POLYCRYSTALLINE REGION THEREUNDER
    Publication number: 20220102480
    Abstract: A structure includes a semiconductor substrate, and a polycrystalline resistor region over the semiconductor substrate. The polycrystalline resistor region includes a semiconductor material in a polycrystalline morphology. A dopant-including polycrystalline region is between the polycrystalline resistor region and the semiconductor substrate.
    Type: Application
    Filed: September 29, 2020
    Publication date: March 31, 2022
    Inventors: Yves T. Ngu, Siva P. Adusumilli, Steven M. Shank, Michael J. Zierak, Mickey H. Yu
  • SEMICONDUCTOR STRUCTURES WITH BODY CONTACT REGIONS EMBEDDED IN POLYCRYSTALLINE SEMICONDUCTOR MATERIAL
    Publication number: 20220093744
    Abstract: Body-contacted semiconductor structures and methods of forming a body-contacted semiconductor structure. A semiconductor substrate, which contains of a single-crystal semiconductor material, includes a device region and a plurality of body contact regions each comprised of the single-crystal semiconductor material. A polycrystalline layer and polycrystalline regions are formed in the semiconductor substrate. The polycrystalline regions are positioned between the polycrystalline layer and the device region, and the polycrystalline regions have a laterally-spaced arrangement with a gap between each adjacent pair of the polycrystalline regions. One of the plurality of body contact regions is arranged in the gap between each adjacent pair of the polycrystalline regions.
    Type: Application
    Filed: September 23, 2020
    Publication date: March 24, 2022
    Inventors: Steven M. Shank, Siva P. Adusumilli, Yves Ngu, Michael Zierak
  • Trench-based photodiodes
    Patent number: 11282883
    Abstract: Structures including a photodiode and methods of fabricating such structures. A trench extends from a top surface of a substrate to a depth into the substrate. The photodiode includes an active layer positioned in the trench. Trench isolation regions, which are located in the substrate, are arranged to surround the trench. A portion of the substrate is positioned in a surrounding relationship about the active layer and between the active layer and the trench isolation regions.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: March 22, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: John J. Ellis-Monaghan, Steven M. Shank, Vibhor Jain, Anthony K. Stamper, John J. Pekarik
  • Wafer with crystalline silicon and trap rich polysilicon layer
    Patent number: 11271079
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a wafer with crystalline silicon and trap rich polysilicon layer and methods of manufacture. The structure includes: semiconductor-on-insulator (SOI) wafer composed of a lower crystalline semiconductor layer, a polysilicon layer over the lower crystalline semiconductor layer, an upper crystalline semiconductor layer over the polysilicon layer, a buried insulator layer over the upper crystalline semiconductor layer, and a top crystalline semiconductor layer over the buried insulator layer.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: March 8, 2022
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Anthony K. Stamper, Steven M. Shank, John J. Pekarik, Vibhor Jain, John J. Ellis-Monaghan
  • Trap-rich layer in a high-resistivity semiconductor layer
    Patent number: 11271077
    Abstract: Structures including electrical isolation and methods of forming a structure including electrical isolation. A semiconductor layer is formed over a semiconductor substrate and shallow trench isolation regions are formed in the semiconductor layer. The semiconductor layer includes single-crystal semiconductor material having an electrical resistivity that is greater than or equal to 1000 ohm-cm. The shallow trench isolation regions are arranged to surround a portion of the semiconductor layer to define an active device region. A polycrystalline layer is positioned in the semiconductor layer and extends laterally beneath the active device region and the shallow trench isolation regions that surround the active device region.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: March 8, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Anthony K. Stamper, Vibhor Jain, John J. Pekarik, Steven M. Shank, John J. Ellis-Monaghan
  • DEVICE COMPRISING AN OPTOFLUIDIC SENSOR WITH INTEGRATED PHOTODIODE
    Publication number: 20220062896
    Abstract: One illustrative device disclosed herein includes a semiconductor substrate, a channel that is at least partially defined by at least a portion of the semiconductor substrate, an input fluid reservoir and an output fluid reservoir, wherein the channel is in fluid communication with the input fluid reservoir and the output fluid reservoir. In this example, the device further includes a first radiation source operatively coupled to the substrate, wherein the first radiation source is adapted to generate radiation in a direction toward the channel, and at least one photodiode positioned adjacent the channel.
    Type: Application
    Filed: August 28, 2020
    Publication date: March 3, 2022
    Inventors: Steven M. Shank, Vibhor Jain, Anthony Stamper, John Pekarik, John Ellis-Monaghan, Ramsey Hazbun
  • Isolation trenches augmented with a trap-rich layer
    Patent number: 11264457
    Abstract: Semiconductor structures with electrical isolation and methods of forming a semiconductor structure with electrical isolation. A shallow trench isolation region, which contains a dielectric material, is positioned in a semiconductor substrate. A trench extendes through the shallow trench isolation region and to a trench bottom in the semiconductor substrate beneath the shallow trench isolation region. A dielectric layer at least partially fills the trench. A polycrystalline region, which is arranged in the semiconductor substrate, includes a portion that is positioned beneath the trench bottom.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: March 1, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Mark Levy, Siva P. Adusumilli, Steven M. Shank, Alvin J. Joseph, Anthony K. Stamper
  • Transistor devices with source/drain regions comprising an interface layer that comprises a non-semiconductor material
    Patent number: 11264499
    Abstract: One illustrative transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate and a source region and a drain region, each of which comprise an epi cavity with a bottom surface and a side surface. The transistor further includes an interface layer positioned on at least one of the side surface and the bottom surface of the epi cavity in each of the source/drain regions, wherein the interface layer comprises a non-semiconductor material and an epi semiconductor material positioned on at least an upper surface of the interface layer in the epi cavity in each of the source region and the drain region.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: March 1, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: John J. Pekarik, Steven M. Shank, Anthony K. Stamper, Vibhor Jain, John Ellis-Monaghan
  • TRANSISTOR WITH EMBEDDED ISOLATION LAYER IN BULK SUBSTRATE
    Publication number: 20220028971
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a transistor with an embedded isolation layer in a bulk substrate and methods of manufacture. The structure includes: a bulk substrate; an isolation layer embedded within the bulk substrate and below a top surface of the bulk substrate; a deep trench isolation structure extending through the bulk substrate and contacting the embedded isolation layer; and a gate structure over the top surface of the bulk substrate and vertically spaced away from the embedded isolation layer, the deep trench isolation structure and the embedded isolation layer defining an active area of the gate structure in the bulk substrate.
    Type: Application
    Filed: July 27, 2020
    Publication date: January 27, 2022
    Inventors: Uzma RANA, Anthony K. STAMPER, Johnatan A. KANTAROVSKY, Steven M. SHANK, Siva P. ADUSUMILLI