Patents by Inventor Steven T. McClure

Steven T. McClure has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7178146
    Abstract: Described are techniques used in task scheduling to form a run list used by a task scheduler. A non-priority based technique is disclosed in which each task to be executed is allotted a “pie” count representing the number of times out of the total run list each task is considered for scheduling. The total run list is the sum of all the “pie” counts for all tasks. Each time a task starts, exits, or has its pie count reset, the total number of “pie” counts is computed and tasks are distributed throughout the run list. Each task is distributed in the run list in accordance with its number of “pie” counts such that a minimum number of intervening tasks appears between each successive appearance of the same task. The computed run list is then used by the scheduler. The task scheduling techniques disclosed may be used in a data storage system or elsewhere in a computer system.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: February 13, 2007
    Assignee: EMC Corporation
    Inventors: Steven T. McClure, Steven R. Chalmer, Brett D. Niver
  • Patent number: 7136969
    Abstract: Described is a technique for maintaining local cache coherency between endpoints using the connecting message fabric. Processors in a data storage system communicate using the message fabric. Each processor is an endpoint having its own local cache storage in which portions of global memory may be locally cached. A write through caching technique is described. Each local cache line of data of each processor is either in an invalid or a shared state. When a write to global memory is performed by a processor (write miss or a write hit), the following are performed atomically: the global memory is updated, other processor's local cache lines of the data are invalidated, verification of invalidation is received by the processor, and the processor's local copy is updated. Other processors' cache lines are invalidated by transmission of an invalidate command by the processor. A processor updates its local cache lines upon the next read miss or write miss of the updated cacheable global memory.
    Type: Grant
    Filed: June 17, 2003
    Date of Patent: November 14, 2006
    Assignee: EMC Corporation
    Inventors: Brett D. Niver, Steven R. Chalmer, Steven T. McClure
  • Patent number: 7085781
    Abstract: A memory storage device has a file storage operating system which uses an inode to record and find segments of each data file. The inode includes a plurality of rows. A portion of the rows are written with direct extents pointing to data blocks storing portions of file segments. At least two of the extents point to data blocks having addresses in different logical volumes.
    Type: Grant
    Filed: November 24, 2003
    Date of Patent: August 1, 2006
    Assignee: EMC Corporation
    Inventors: Preston F. Crow, Robert S. Mason, Jr., Steven T. McClure, Susan C. Nagy, Richard G. Wheeler
  • Patent number: 6895418
    Abstract: A memory storage device has a file storage operating system that uses inodes to access file segments. Each inode has a plurality of rows. A portion of the rows can store extents pointing, directly or indirectly, to data blocks. Each extent has a field to indicate whether the extent is an indirect extent or a direct extent.
    Type: Grant
    Filed: April 28, 1999
    Date of Patent: May 17, 2005
    Assignee: EMC Corporation
    Inventors: Preston F. Crow, Robert S. Mason, Jr., Steven T. McClure, Susan C. Nagy, Richard G. Wheeler
  • Publication number: 20040254907
    Abstract: A memory storage device has a file storage operating system that uses inodes to access file segments. Each inode has a plurality of rows. A portion of the rows can store extents pointing, directly or indirectly, to data blocks. Each extent has a field to indicate whether the extent is an indirect extent or a direct extent.
    Type: Application
    Filed: August 20, 2003
    Publication date: December 16, 2004
    Inventors: Preston F. Crow, Robert S. Mason, Steven T. McClure, Susan C. Nagy, Richard G. Wheeler
  • Patent number: 6757790
    Abstract: The data storage facility includes a plurality of data storage devices coupled through multi-path connections to cache memory. A plurality of interfaces to host processors communicates with the cache memory and with cache tag controllers that define the cache memory again over multiple paths.
    Type: Grant
    Filed: February 19, 2002
    Date of Patent: June 29, 2004
    Assignee: EMC Corporation
    Inventors: Steven R. Chalmer, Steven T. McClure, Brett D. Niver, Richard G. Wheeler
  • Publication number: 20040105332
    Abstract: A memory storage device has a file storage operating system which uses an inode to record and find segments of each data file. The inode includes a plurality of rows. A portion of the rows are written with direct extents pointing to data blocks storing portions of file segments. At least two of the extents point to data blocks having addresses in different logical volumes.
    Type: Application
    Filed: November 24, 2003
    Publication date: June 3, 2004
    Inventors: Preston F. Crow, Robert S. Mason, Steven T. McClure, Susan C. Nagy, Richard G. Wheeler
  • Patent number: 6728962
    Abstract: Disclosed is context swapping in a multitasking operating system for a processor that includes providing a plurality of context blocks for storing context information for a plurality of processes, providing an array of pointers to the context blocks, providing an index to the array of pointers, and swapping context by adjusting at least one pointer in the array of pointers to point to a context block of a new process. Further included may be incrementing the index prior to adjusting the at least one pointer in the array of pointers. Further included may be, after adjusting at least one pointer in the array of pointers, decrementing the index and causing the processor to jump to an address indicated by a program counter value of the new process. The context information may include values for registers, a stack pointer, and a program counter for a process.
    Type: Grant
    Filed: June 28, 2000
    Date of Patent: April 27, 2004
    Assignee: EMC Corporation
    Inventors: Steven R. Chalmer, Steven T. McClure
  • Patent number: 6687903
    Abstract: Disclosed is inhibiting process starvation in a multitasking operating system by providing a first type of scheduling event at periodic timer intervals, providing a second type of second scheduling event in response to a running processes voluntarily relinquishing the processor, and, in response to a scheduling event, replacing an old process with a new process only if the old process has run for more than a predetermined amount of time. The predetermined amount of time may be one half of the timer interval. The system described herein provides a small kernel that can run on a variety of hardware platforms, such as a PowerPC based Symmetrix adapter board used in a Symmetrix data storage device provided by EMC Corporation of Hopkinton, Mass. The core kernel code may be written for the general target platform, such as the PowerPC architecture.
    Type: Grant
    Filed: June 28, 2000
    Date of Patent: February 3, 2004
    Assignee: EMC Corporation
    Inventors: Steven R. Chalmer, Steven T. McClure, Brett D. Niver
  • Patent number: 6654772
    Abstract: A memory storage device has a file storage operating system which uses an inode to record and find segments of each data file. The inode includes a plurality of rows. A portion of the rows are written with direct extents pointing to data blocks storing portions of file segments. At least two of the extents point to data blocks having addresses in different logical volumes.
    Type: Grant
    Filed: April 28, 1999
    Date of Patent: November 25, 2003
    Assignee: EMC Corporation
    Inventors: Preston F. Crow, Robert S. Mason, Jr., Steven T. McClure, Susan C. Nagy, Richard G. Wheeler
  • Publication number: 20030159001
    Abstract: The data storage facility includes a plurality of data storage devices coupled through multi-path connections to cache memory. A plurality of interfaces to host processors communicates with the cache memory and with cache tag controllers that define the cache memory again over multiple paths.
    Type: Application
    Filed: February 19, 2002
    Publication date: August 21, 2003
    Inventors: Steven R. Chalmer, Steven T. McClure, Brett D. Niver, Richard G. Wheeler