Abstract: According to an example, a device may comprise a printed circuit board. The printed circuit board may further comprise a first layer and a second layer. The first layer may comprise a first material and the second layer may comprise a second material. In some examples, the first layer may further comprise at least one mounting hole surrounded by a third material at a thickness equal to a thickness of the first layer, and the first material may be electrically isolated from the third material. In some examples, the printed circuit board may be mated to a light guide assembly for a touchscreen system.

Abstract: According to an example, a device may comprise a touchscreen light guide assembly, a lens disposed on the touchscreen light guide assembly, and a printed circuit board including a relief cut on an edge of the printed circuit board. The relief cut may be to receive the touchscreen light guide assembly and to allow the lens to extend into the printed circuit board relief cut.

Abstract: According to an example, a device may comprise a printed circuit board. The printed circuit board may further comprise a first layer and a second layer, The first layer may comprise a first material and the second layer may comprise a second material. In some examples, the first layer may further comprise at least one mounting hole surrounded by a third material at a thickness equal to a thickness of the first layer, and the first material may be electrically isolated from the third material, In some examples, the printed circuit board may be mated to a light guide assembly for a touchscreen system.

Abstract: According to an example, a device may comprise a touchscreen light guide assembly, a lens disposed on the touchscreen light guide assembly, and a printed circuit board including a relief cut on an edge of the printed circuit board. The relief cut may be to receive the touchscreen light guide assembly and to allow the lens to extend into the printed circuit board relief cut.

Abstract: Systems and methods for transferring data between a host device and a storage medium are provided. In one implementation, a system for transferring data between a host device and a storage medium includes a host interface that receives from the host device a command to transfer data between the host device and the storage medium, a buffer that temporarily stores data that is transferred between the host device and the storage medium, a first register that stores a value for tracking a number of data units that have been transferred into the buffer but that have not yet been transferred out of the buffer, a second register that stores a value for incrementing a value contained in the first register, and a third register that stores a value for decrementing a value contained in the first register.

Abstract: A system for error correction coding and decoding information is disclosed. In one embodiment, the first and second encoders are each configured to encode the information, wherein the second encoder has a higher capability than the first encoder. First and second decoders are configured to recover the information, wherein the second decoder recovers the information encoded by the second encoder only if the first decoder cannot recover the information.

Abstract: A memory card comprising a first modular component that comprises a first interface and first conductors and a data mover that comprises second conductors coupled to the first conductors. The first modular component is replaceable with a second modular component that comprises a second interface that differs from the first interface and third conductors that are configured to couple to the second conductors.

Abstract: A system comprises a storage controller for managing transfers of data between a host and storage memory; a data mover coupled to the storage controller handling data transferred between a host and storage memory; and a buffer coupled to the data mover for storing data being transferred. The storage controller modifies operation of the storage system based on status of the data transfer. An associate method comprises transferring data between a host and storage memory via a storage system, and dynamically adjusting operation of the storage system depending on status of the data transfer.

Abstract: Embodiments of the present invention are implemented in memory systems. In one embodiment, the memory comprises an array of memory cells and a control circuit. The control circuit is configured to read error correction coded data from the array of memory cells, provide error correction code decoding to selected error correction coded data and discard unused error correction code parity data of unselected error correction coded data.

Abstract: Methods and systems are provided for transferring data and for pausing the transfer of data when certain conditions are met. In one embodiment, an error correcting code (ECC) encoder/decoder reads a codeword from a data storage device and decodes the codeword. The ECC encoder/decoder corrects any correctable errors in the codeword and outputs information regarding the condition of the codeword, such as the number of detected full errors and the number of erasures. The number of full errors is compared with a full error threshold value. When erasures are available, the number of erasures can be compared with an erasure threshold value. Both threshold values may be set at levels below the maximum levels at which errors can still be corrected. When either of the threshold values are exceeded, the transfer of data is paused and a processor is interrupted so that further action may be taken.

Abstract: A fault-tolerant magnetoresistive solid-state storage device (MRAM) in use performs error correction coding and decoding of stored information, to tolerate physical defects. At manufacture, the MRAN device is tested to confirm that each set of storage cells is suitable for storing ECC encoded data, using either a parametric evaluation (step 602), or a logical evaluation (step 603) or preferably a combination of both. Failed cells are identified and a count is formed, suitably in terms of ECC symbols 206 that would be affected by such failed cells (step 604). The count can be compared to a threshold (step 605) to determine suitability of the accessed storage cells and a decision made (step 606) on whether to continue with use of those cells, or whether to take remedial action.

Abstract: A device comprises a memory array in which a plurality of codewords is stored. Each codeword comprises an error correction code and a data block that comprises a plurality of units of data. The device further comprises an error code correction module coupled to the memory array. When multiple units of data are to be read from the device for an address, a codeword stored in a location associated with the address is fetched from the memory array, the error code correction module decodes the codeword and corrects any errors in the data block for that codeword, and the multiple units of data are read from the corrected data block.

Abstract: A magnetoresistive solid-state storage device (MRAM) employs error correction coding (ECC) to form ECC encoded stored data. In a read operation, parametric values are obtained from storage cells 16 of the device and compared to ranges to establish logical bit values, together with erasure information. The erasure information identifies symbols 206 in a block of ECC encoded data 204 which, from the parametric evaluation, are suspected to be affected by physical failures of the storage cells 16. Where the position of suspected failed symbols 206 is known from this erasure information, the ability of a decoder 22 to perform ECC decoding is substantially enhanced.

Abstract: Systems and methods for controlling communication with nonvolatile memory devices via a memory bus are provided. Briefly described, one of many possible embodiments is a system comprising a memory controller in communication with a memory bus, the memory controller configured to control communication with at least one nonvolatile memory device by configuring the at least one nonvolatile memory device, via the memory bus, with a unique device identifier.

Abstract: The present invention relates to a storage device controller for controlling the operations of the data storage system. The controller includes error-correcting code (ECC) coding and decoding of data stored on media of the data storage system. A Verify procedure of the present invention is performed which verifies the validity of the data written to the media. The Verify procedure runs continuously until an error is detected or until an external event terminates the procedure. By accessing a range of memory addresses in the media and by resetting an address counter to a start of the range of addresses after a last address of the range has been accessed, the Verify procedure continuously checks the memory locations for errors. The range of addresses may include all of the accessible addresses in the data storage device. Additionally, information on the quality of the media may be collected and used to determine how much the media deteriorates over time.

Abstract: A data storage device comprising a first memory cell string that includes at least a first magnetic random access memory (MRAM) cell coupled to a second MRAM cell and a circuit coupled to a node between the first MRAM cell and the second MRAM cell is provided. The circuit is configured to detect a voltage change at the node in response to a voltage being provided to the memory cell string and in response to a write sense current being applied across the first MRAM cell.

Abstract: A data storage device that includes a memory cell string. The memory cell string includes a first memory cell and a second memory cell. The device also includes a circuit coupled to a node between the first memory cell and a second memory cell. The circuit is configured to detect a voltage change at the node in response to a voltage being provided to the memory cell string and the first memory cell being written to a first state.

Abstract: In a data storage and retrieval system, a method and system for exchanging operation parameters between a data storage device and a storage device controller is disclosed. A memory device within the data storage device comprises operation parameter registers, which store operation parameters that are indicative of environmental conditions and characteristics of the memory device itself. The operation parameter registers may be readable and writable. To initiate an exchange of operation parameters, the storage device controller sends a command code indicative of an operation parameter exchange command and designates an address in the operation parameter registers to which operation parameters are to be written or from which operation parameters are to be read.

Abstract: Systems and methods for transferring data between a host device and a storage medium are provided. In one implementation, a method for transferring data between a host device and a storage medium includes receiving from the host device a command to transfer data between the host device and a storage medium, storing in a first register a value that is correlated to a number of second data units contained in a first data unit, and storing in a second register a value for tracking a number of second data units that are transferred between the host device and a buffer.

Abstract: Systems and methods for transferring data between a host device and a storage medium are provided. In one implementation, a system for transferring data between a host device and a storage medium includes a host interface that receives from a host device a command to transfer data between the host device and the storage medium, a buffer that temporarily stores data that is transferred between the host device and the storage medium, a first register that stores a value for tracking a number of data units that are transferred between the buffer and the storage medium, and a second register that stores a value for tracking a number of data units that are transferred between the host device and the buffer. A data unit is transferred between the buffer and the storage medium if the value in the first register is within a predetermined range. Similarly, a data unit is transferred between the buffer and the host device if the value in the second register is within a predetermined range.