Abstract: A system, circuit, and method for implementing a low power common electrode voltage for a display (e.g., LcoS display) having transistors with low to moderate breakdown voltages may include a first and a second low voltage amplifier, wherein the first amplifier generates a pixel voltage and the second amplifier generates a predetermined voltage. The circuit may include a common electrode circuit coupled to the first and second amplifier to generate a common electrode voltage. Particularly, the circuit may include a control circuit coupled to the common electrode circuit, wherein, during a first phase, the control circuit selectively controls the common electrode circuit to generate a low common electrode voltage based upon a negative value of the predetermined voltage. Further, during a second phase, the control circuit selectively controls the common electrode circuit to generate a high common electrode voltage based upon the sum of the predetermined voltage and the pixel voltage.

Abstract: A system, circuit, and method for implementing a low power common electrode voltage for a display (e.g., LcoS display) having transistors with low to moderate breakdown voltages may include a first and a second low voltage amplifier, wherein the first amplifier generates a pixel voltage and the second amplifier generates a predetermined voltage. The circuit may include a common electrode circuit coupled to the first and second amplifier to generate a common electrode voltage. Particularly, the circuit may include a control circuit coupled to the common electrode circuit, wherein, during a first phase, the control circuit selectively controls the common electrode circuit to generate a low common electrode voltage based upon a negative value of the predetermined voltage. Further, during a second phase, the control circuit selectively controls the common electrode circuit to generate a high common electrode voltage based upon the sum of the predetermined voltage and the pixel voltage.

Abstract: An amplifier circuit including a first folded double cascode stage configured to receive a differential input signal at a first pair of input transistors and generate a first drive signal, a second folded double cascode stage configured to receive the differential input signal at a second pair of input transistors and generate a second drive signal, and an output stage. The output stage includes a PMOS common-source output transistor configured to receive the first drive signal at its gate, and an NMOS common-source output transistor configured to receive the first drive signal at its gate, the PMOS common-source output transistor and NMOS common-source output transistor being jointly configured to generate an output signal based on the first drive signal and the second drive signal.

Abstract: A system, circuit, and method for implementing a low power common electrode voltage for a display (e.g., LcoS display) having transistors with low to moderate breakdown voltages may include a first and a second low voltage amplifier, wherein the first amplifier generates a pixel voltage and the second amplifier generates a predetermined voltage. The circuit may include a common electrode circuit coupled to the first and second amplifier to generate a common electrode voltage. Particularly, the circuit may include a control circuit coupled to the common electrode circuit, wherein, during a first phase, the control circuit selectively controls the common electrode circuit to generate a low common electrode voltage based upon a negative value of the predetermined voltage. Further, during a second phase, the control circuit selectively controls the common electrode circuit to generate a high common electrode voltage based upon the sum of the predetermined voltage and the pixel voltage.

Abstract: Systems and methods for a digital pixel circuit for liquid crystal displays are provided. The design includes a dual-voltage pixel design, a two-transistor level-shift circuit design, self-adjusting transistor bias circuitry; and an optional on-chip test-array to determine die-specific design-center values for critical transistor leakage and threshold parameters. Level shift design simplicity, small pixel pitch, and applicability for small display applications such as microdisplays, are among the various benefits and advantages obtained.

Abstract: A system, circuit, and method for implementing a low power common electrode voltage for a display (e.g., LcoS display) having transistors with low to moderate breakdown voltages may include a first and a second low voltage amplifier, wherein the first amplifier generates a pixel voltage and the second amplifier generates a predetermined voltage. The circuit may include a common electrode circuit coupled to the first and second amplifier to generate a common electrode voltage. Particularly, the circuit may include a control circuit coupled to the common electrode circuit, wherein, during a first phase, the control circuit selectively controls the common electrode circuit to generate a low common electrode voltage based upon a negative value of the predetermined voltage. Further, during a second phase, the control circuit selectively controls the common electrode circuit to generate a high common electrode voltage based upon the sum of the predetermined voltage and the pixel voltage.

Abstract: A system, circuit, and method for implementing a low power common electrode voltage for a display (e.g., LcoS display) having transistors with low to moderate breakdown voltages may include a first and a second low voltage amplifier, wherein the first amplifier generates a pixel voltage and the second amplifier generates a predetermined voltage. The circuit may include a common electrode circuit coupled to the first and second amplifier to generate a common electrode voltage. Particularly, the circuit may include a control circuit coupled to the common electrode circuit, wherein, during a first phase, the control circuit selectively controls the common electrode circuit to generate a low common electrode voltage based upon a negative value of the predetermined voltage. Further, during a second phase, the control circuit selectively controls the common electrode circuit to generate a high common electrode voltage based upon the sum of the predetermined voltage and the pixel voltage.

Abstract: A system, circuit, and method for implementing a low power common electrode voltage for a display (e.g., LCoS display) having transistors with low to moderate breakdown voltages may include a first and a second low voltage amplifier, wherein the first amplifier generates a pixel voltage and the second amplifier generates a predetermined voltage. The circuit may include a common electrode circuit coupled to the first and second amplifier to generate a common electrode voltage. Particularly, the circuit may include a control circuit coupled to the common electrode circuit, wherein, during a first phase, the control circuit selectively controls the common electrode circuit to generate a low common electrode voltage based upon a negative value of the predetermined voltage. Further, during a second phase, the control circuit selectively controls the common electrode circuit to generate a high common electrode voltage based upon the sum of the predetermined voltage and the pixel voltage.

Abstract: A system, circuit, and method for implementing a low power common electrode voltage for a display (e.g., LCoS display) having transistors with low to moderate breakdown voltages may include a first and a second low voltage amplifier, wherein the first amplifier generates a pixel voltage and the second amplifier generates a predetermined voltage. The circuit may include a common electrode circuit coupled to the first and second amplifier to generate a common electrode voltage. Particularly, the circuit may include a control circuit coupled to the common electrode circuit, wherein, during a first phase, the control circuit selectively controls the common electrode circuit to generate a low common electrode voltage based upon a negative value of the predetermined voltage. Further, during a second phase, the control circuit selectively controls the common electrode circuit to generate a high common electrode voltage based upon the sum of the predetermined voltage and the pixel voltage.

Abstract: Disclosed is an apparatus including a transmitter amplifier having an output terminal communicatively coupled to a transmission line to output a first set of radio frequency (RF) signals to an antenna. The apparatus may include a receiver amplifier having an input terminal communicatively coupled to the transmission line to receive a second set of RF signals from the antenna. The apparatus may include a passive network coupled between the transmitter amplifier and the receiver amplifier, the passive network being configurable to cancel either a first reactance of a parasitic capacitance of the transmitter amplifier or second reactance of a parasitic capacitance of the receiver amplifier. The apparatus may also include a switch coupled between the input terminal and a voltage reference to selectively configure the passive network to cancel either the first reactance or the second reactance. Other embodiments may be described and claimed.

Abstract: Embodiments of apparatuses, articles, methods, and systems for calibrating receive chain to reduce second order intermodulation distortion are disclosed herein. In some embodiments, a reference sensing chain is used to generate reference second-order intermodulation distortion signals that may be used to adjust a calibration code. In some embodiments, a calibration code may be adjusted using one or more feedback loops of a baseband amplifier. The embodiments may be employed, e.g., to manage power in wireless networks. Other embodiments and usages may be described and claimed.

Abstract: Embodiments of a high-linearity low-noise amplifier (LNA) are generally described herein. Other embodiments may be described and claimed. In some embodiments, an RF input signal may be amplified with a cascode amplifier. The cascode amplifier may include integrated notch filters to attenuate undesired signals. The cascode amplifier may operate from a large power supply when blockers are present to avoid voltage swing compression at its output. The cascode amplifier may be biased and designed to operate in a class AB mode to produce linear output current to avoid current compression or excessive current expansion.

Abstract: Embodiments of the present invention include a low phase noise oscillator circuit using a current-reuse technique to reduce power consumption and improve phase noise, where the oscillator circuit comprises a first VCO coupled to a second VCO, and the outputs of the first and second VCOs are coupled with passive elements, such as capacitors. The overall power consumption of both the first and second VCOs is about the same as a single VCO. Furthermore, the phase noise is lowered by around 3 dB. Thus, the phase noise performance is improved without increasing the power consumption of the oscillator circuit.

Abstract: Embodiments of the present invention include a low phase noise oscillator circuit using a current-reuse technique to reduce power consumption and improve phase noise, where the oscillator circuit comprises a first VCO coupled to a second VCO, and the outputs of the first and second VCOs are coupled with passive elements, such as capacitors. The overall power consumption of both the first and second VCOs is about the same as a single VCO. Furthermore, the phase noise is lowered by around 3 dB.

Abstract: A wireless device includes high-performance CMOS RF switches that include serially connected transistors coupled between an input terminal and an output terminal, with an inductor coupled from the input to the output that resonates out the capacitance of the transistors to improve isolation. The transistors have a floating/bootstrapped body with remote body contacts.

Abstract: Embodiments of a high-linearity low-noise amplifier (LNA) are generally described herein. Other embodiments may be described and claimed. In some embodiments, an RF input signal may be amplified with a cascode amplifier. The cascode amplifier may include integrated notch filters to attenuate undesired signals. The cascode amplifier may operate from a large power supply when blockers are present to avoid voltage swing compression at its output. The cascode amplifier may be biased and designed to operate in a class AB mode to produce linear output current to avoid current compression or excessive current expansion.

Abstract: A dual reactive shunt feedback low noise amplifier design may include a transconductance amplifier having a capacitor coupled across it and a pair of coupled inductors coupled across it. In one embodiment, the coupled inductors may be laid out as two overlapping coils.

Abstract: A gate-to-source voltage (Vgs) replication circuit includes a diode-connected NMOS transistor coupled to a current source to draw a drain-to-source current therethrough. The generated Vgs is imposed across a source-to-gate junction of a PMOS transistor. A second PMOS transistor is coupled in series with the first PMOS transistor such that the source-to-gate voltage (Vsg) of the second PMOS transistor replicates the Vgs of the NMOS circuit. The second PMOS transistor is coupled as a source follower to bias other NMOS transistors.

Abstract: An apparatus for transmitter control is disclosed. The apparatus includes an analog circuit designed to operate on at least a portion of a communications signal to be wirelessly transmitted, based at least in part on a control signal. The apparatus includes a lookup table coupled to the analog circuit, with the lookup table designed to output the control signal based at least in part on the communications signal, or one or more measured metrics of the communications signal. Embodiments of the present invention include, but are not limited to, methods encompassing the operations described above, as well as subsystems and systems designed to operate in the above described manner.

Abstract: Embodiments of apparatuses, articles, methods, and systems for calibrating receive chain to reduce second order intermodulation distortion are disclosed herein. The embodiments may be employed, e.g., to manage power in wireless networks. Other embodiments and usages may be described and claimed.