Abstract: A vertical semiconductor device includes; a pattern structure including a plurality of insulation patterns and a plurality of gate electrodes that are alternately and repeatedly stacked on a substrate, wherein the pattern structure includes a first gate electrode serving as a gate electrode of an erase transistor, wherein the first gate electrode is one of the plurality of gate electrodes; and a channel structure in a channel hole passing through the pattern structure, wherein the channel structure includes a data storage structure, a first channel, an undoped semiconductor liner, a doped semiconductor pattern, a filling insulation pattern and a capping pattern, wherein the data storage structure, the first channel, the undoped semiconductor liner, and the doped semiconductor pattern are sequentially disposed on a sidewall of the first gate electrode.

Abstract: An inspection apparatus includes an inspection signal source configured to irradiate a wafer with an inspection ray having a frequency in a range of 0.1 terahertz (THz) to 10 THz, a curved rail, a probe mount configured to move along the curved rail, and first and second probes coupled to the probe mount, wherein the first probe is configured to detect the inspection ray transmitted through the wafer, and the curved rail has a curved surface convex toward the first and second probes.

Abstract: A memory device includes a plurality of sub-array areas each including a plurality of memory cells, a plurality of contact areas located between the plurality of sub-array areas, a plurality of word lines each extending in a first direction to cross the plurality of sub-array areas and the plurality of contact areas, and a plurality of sub-word line drivers beneath the plurality of sub-array areas and configured to drive the plurality of word lines, wherein each of the plurality of contact areas comprises a plurality of contacts electrically connecting a corresponding word line, among the plurality of word lines, to a sub-word line driver.

Abstract: A read-out circuit includes an operational amplifier configured to receive an input voltage through a positive input terminal; a feedback capacitor connected between an output terminal of the operational amplifier and a negative input terminal of the operational amplifier; a sensor charging and discharging circuit configured to charge or discharge a sensor during a first time; a switching circuit connecting the sensor and the operational amplifier during a second time after the sensor is charged or discharged; and a duty control circuit configured to determine a duty ratio of the first time and the second time according to a capacitance of the sensor.

Abstract: A polymer electrolyte is provided, which includes a polymer including an ethylene oxide unit; and a lithium salt, wherein the terminal of the polymer is substituted with one to four functional groups selected from the group consisting of a nitrogen compound functional group and phosphorus compound functional group, and the terminal of the polymer and the one to four functional groups are linked by one selected from the group consisting of a C2 to C20 alkylene linker, a C2 to C20 ether linker, and a C2 to C20 amine linker. A method for preparing the same is also provided.

Abstract: A phase mixing circuit for a multi-phase signal includes a jitter cancellation circuit configured to mix phases of a signal input to a first node and a signal input to a second node to produce signals at a third node and a fourth node; and a delay adjustment circuit configured to adjust delays of the signals output from the third node and the fourth node to produce signals at a fifth node and a sixth node.

Abstract: A phase mixing circuit for a multi-phase signal includes a jitter cancellation circuit configured to mix phases of a signal input to a first node and a signal input to a second node to produce signals at a third node and a fourth node; and a delay adjustment circuit configured to adjust delays of the signals output from the third node and the fourth node to produce signals at a fifth node and a sixth node.

Abstract: An amplifier includes an amplification circuit including an input circuit receiving an input signal and configured to output an output signal by amplifying the input signal; and an offset cancelling circuit configured to cancel offset by controlling the input circuit according to activation control signal and offset control signal, wherein the offset cancelling circuit cancels the offset according to the offset control signal after the activation control signal is activated.

Abstract: A current sensing topology uses an amplifier with capacitively coupled inputs in feedback to sense the input offset of the amplifier, which can be compensated for during measurement. The amplifier with capacitively coupled inputs in feedback is used to: operate the amplifier in a region where the input common-mode specifications are relaxed, so that the feedback loop gain and/or bandwidth is higher; operate the sensor from the converter input voltage by employing high-PSRR (power supply rejection ratio) regulators to create a local, clean supply voltage, causing less disruption to the power grid in the switch area; sample the difference between the input voltage and the controller supply, and recreate that between the drain voltages of the power and replica switches; and compensate for power delivery network related (PDN-related) changes in the input voltage during current sensing.

Abstract: Disclosed is a method of operating a storage controller which communicates with a host and a non-volatile memory device. The method includes receiving a first state transition request for a device open from the host, performing a first active zone refresh operation of the non-volatile memory device in response to the first state transition request such that a zone, which has an active state before an immediately previous power-off is processed to a sequentially writable state in one block, receiving, by a first buffer memory, first target data to be stored in a first block of a first zone among the plurality of zones from the host depending on a first write request, receiving a first power-off request from the host, during processing the first write request, and storing the first target data in a first power loss protection (PLP) block of the non-volatile memory device.

Abstract: A single inductor multiple output DC-to-DC converter may be configured as a buck-boost converter. The converter may include an inductor, a plurality of switches coupled to the inductor to control energizing and deenergizing phases of the inductor, and a plurality of output rails. Each of the plurality of output rails may include at least one switch, which is configured to connect the output rail to the inductor of the buck-boost converter. Depending on the energizing and deenergizing patterns of the inductor, and the state of the one or more switches, the various output rails may be supplied with a plurality of different output voltages and / or output currents. Any of a plurality of regulating strategies may be utilized to further control the output voltages and / or the output currents.

Abstract: A capacitor structure may include a lower electrode on a substrate, a dielectric layer on the substrate, and an upper electrode on the dielectric layer. The lower electrode may include a metal nitride having a chemical formula of M1Ny (M1 is a first metal, and y is a positive real number). The dielectric layer may include a metal oxide and nitrogen (N), the metal oxide having a chemical formula of M2Ox (M2 is a second metal, and x is a positive real number). A maximum value of a detection amount of nitrogen (N) in the dielectric layer may be greater than a maximum value of a detection amount of nitrogen (N) in the lower electrode.

Abstract: A digital control scheme controls an integrator of a PID filter to implement non-linear control of saturating the duty cycle during which the proportional and derivative terms of the PID filter are set to 0 while the integrator and its internal states (previous values or memory) is set to a duty cycle that is the sum of the current nominal duty cycle plus a deltaD. The deltaD is the maximum duty cycle increment that is used to regulate a voltage regulator from ICCmin to ICCmax and is a configuration register that can be set post silicon. An FSM moves from a non-linear all ON state to an open loop duty cycle which maintains the output voltage slightly higher than the required Vref. After a certain period in this open loop, the FSM then ramps down the open loop duty cycle value until the output voltage is close to the Vref.

Abstract: An operating method of a data storge device including a buffer memory, a non-volatile memory, and a controller, includes receiving, from a host, an encryption request for data stored in the buffer memory, and performing an encryption operation in response to the encryption request, wherein the performing of the encryption operation comprises performing a program operation, the performing of the program operation comprises receiving a physical address of a buffer region of the non-volatile memory, generating encrypted data by causing an encryption module included in the controller to be in an on state to encrypt the data stored in the buffer memory, and programming the encrypted data in the buffer region of the non-volatile memory based on the physical address.

Abstract: Disclosed is a composition for preventing or inhibiting influenza virus infection, containing ginseng berry polysaccharides as active ingredients, and the ginseng berry polysaccharides exhibit an inhibitory effect on influenza virus activity or infection due to specific ingredients and structures and, specifically, have an excellent inhibitory effect on neuraminidase activity.

Abstract: An electrochemical pretreatment method of a vanadium positive electrode for a lithium secondary battery, which can improve the lifetime characteristics of the positive electrode and the battery by inhibiting the leaching of vanadium when charging and discharging the lithium secondary battery using, for instance, vanadium oxide (V2O5) as a positive electrode, and a vanadium positive electrode for a lithium secondary battery pretreated thereby. The electrochemical pretreatment method of the vanadium positive electrode for a lithium secondary battery includes a) a step of discharging the lithium free vanadium positive electrode at a voltage of 1.9 V or more; b) an electrochemical pretreatment step of maintaining the discharged vanadium positive electrode of a) at an onset potential value or a potential value having a maximum current through a potentiostat; and c) a step of charging and discharging the pretreated vanadium positive electrode of b) at a voltage range of 2.1V to 4.0V.

Abstract: A dust sensor includes a photo detector configured to detect light scattered from dust; and a signal processing circuit having a high-pass filter receiving an electric signal generated from output of the photo detector. The signal processing circuit generates a dust detection signal using a signal provided to the high-pass filter as well as a signal output from the high-pass filter.

Abstract: A read-out circuit includes an operational amplifier configured to receive input voltage via a positive input terminal; a feedback capacitor connected between an output terminal of the operational amplifier and a negative input terminal of the operational amplifier; a sensor charging/discharging circuit configured to charge or to discharge a sensor capacitor included in a sensor during a first time; and a switching circuit configured to connect the sensor capacitor and the operational amplifier during a second time after the sensor capacitor is charged or discharged.

Abstract: A capacitive transmitter includes a control circuit configured to generate a data signal by delaying input data and to generate a control signal according to the input data and a delayed signal thereof; a capacitor connected between a first node and a transmission node; a driving circuit configured to receive the data signal and to provide an output signal corresponding to the data signal to the first node; and a bias setting circuit configured to set a transmission voltage at the transmission node according to the control signal.

Abstract: A capacitive transmitter includes a control circuit configured to generate a data signal by delaying input data and to generate a control signal according to the input data and a delayed signal thereof; a capacitor connected between a first node and a transmission node; a driving circuit configured to receive the data signal and to provide an output signal corresponding to the data signal to the first node; and a bias setting circuit configured to set a transmission voltage at the transmission node according to the control signal.