Abstract: A method of fabricating a semiconductor device is provided. An initial stack of layers is formed over a substrate. The initial stack alternates between a first material layer and a second material layer that has a different composition from the first material layer. The initial stack is divided into a first stack and a second stack. First GAA transistors are formed in the first stack by using the first material layers as respective channel regions for the first GAA transistors and using the second material layers as respective replacement gates for the first GAA transistors. Second GAA transistors are formed in the second stack by using the second material layers as respective channel regions for the second GAA transistors and using the first material layers as respective replacement gates for the second GAA transistors. The second GAA transistors are vertically offset from the first GAA transistors.

Abstract: A semiconductor device includes: a substrate having a planar surface; a first gate-all-around field effect transistor (GAA-FET) provided on said substrate and comprising a first channel having an untrimmed volume of first channel material corresponding to a volume of the first channel material within a first stacked fin structure from which the first channel was formed; and a second GAA-FET provided on said substrate and comprising a second channel having a trimmed volume of second channel material which is less than said untrimmed volume of first channel material by a predetermined trim amount corresponding to a delay adjustment of the second GAA-FET relative to the first GAA-FET, wherein said first and second GAA FETs are electrically connected as complementary FETs.

Abstract: A method for the dry removal of a material on a microelectronic workpiece is described. The method includes receiving a workpiece having a surface exposing a target layer composed of silicon and either (1) organic material or (2) both oxygen and nitrogen, and selectively removing at least a portion of the target layer from the workpiece. The selective removal includes exposing the surface of the workpiece to a chemical environment containing N, H, and F at a first setpoint temperature to chemically alter a surface region of the target layer, and then, elevating the temperature of the workpiece to a second setpoint temperature to remove the chemically treated surface region of the target layer.

Abstract: A method of fabricating a semiconductor device is provided. The method includes forming BPR structures filled with a replacement BPR material, first S/D structures, first replacement silicide layers, and a pre-metallization dielectric that covers the first replacement silicide layers and the first S/D structures. The method also includes forming first interconnect openings in the pre-metallization dielectric and first replacement interconnect layers in the first interconnect openings. The first replacement interconnect layers are connected to the first replacement silicide layers. A thermal process is executed. The method further includes replacing, from a first side of the first wafer, a first group of the first replacement interconnect layers, a first group of the first replacement silicide layers, and the replacement BPR material, and replacing, from a second side of the first wafer, a second group of the first replacement interconnect layers, and a second group of the first replacement silicide layers.

Abstract: A first source/drain (S/D) structure of a first transistor is formed on a substrate and positioned at a first end of a first channel structure of the first transistor. A first substitute silicide layer is deposited on a surface of the first S/D structure and made of a first dielectric. A second dielectric is formed to cover the first substitute silicide layer and the first S/D structure. A first interconnect opening is formed subsequently in the second dielectric to uncover the first substitute silicide layer. The first interconnect opening is filled with a first substitute interconnect layer, where the first substitute interconnect layer is made of a third dielectric. Further, a thermal processing of the substrate is executed. The first substitute interconnect layer and the first substitute silicide layer are removed. A first silicide layer is formed on the surfaces of the first S/D structure.

Abstract: Embodiments provide a non-plasma etch, such as a gas-phase and/or remote plasma etch, of titanium-containing material layers with tunable selectivity to other material layers. A substrate is received within a process chamber, and the substrate has exposed material layers including a titanium-containing material layer and at least one additional material layer. The additional material layer is selectively etched with respect to the titanium-containing material layer by exposing the substrate to a controlled environment including a halogen-containing gas. For one embodiment, the halogen-containing gas includes a fluorine-based gas. For one embodiment, the titanium-containing material layer is a titanium or a titanium nitride material layer. For one embodiment, the additional material layer includes tungsten, tungsten oxide, hafnium oxide, silicon oxide, silicon-germanium, silicon, silicon nitride, and/or aluminum oxide.

Abstract: A method for the dry removal of a material on a microelectronic workpiece is described. The method includes receiving a substrate having a working surface exposing a silicon-germanium alloy and at least one other material, the silicon-germanium alloy represented as SixGe1-x, wherein x is a real number ranging from 0 to 1; and selectively etching the silicon-germanium alloy relative to the other material by exposing the substrate to a controlled gas-phase environment containing an anhydrous halogen compound, such as a diatomic halogen or an interhalogen compound.

Abstract: Aspects of the disclosure provide a method for forming a semiconductor apparatus. The method includes forming a first field-effect transistor (FET) that includes a first gate on a substrate of the semiconductor apparatus. The method includes forming a second FET that is stacked on the first FET along a direction substantially perpendicular to the substrate and includes a second gate. The method includes forming a first routing track and a second routing track that is electrically isolated from the first routing track. Each of the first and second routing tracks is provided on a routing plane stacked on the second FET along the direction. A first conductive trace configured to conductively couple the first gate of the first FET to the first routing track can be formed. A second conductive trace configured to conductively couple the second gate of the second FET to the second routing track can be formed.

Abstract: A method for the dry removal of a material on a microelectronic workpiece is described. The method includes receiving a substrate having a working surface exposing a metal layer and having at least one other material exposed or underneath the metal layer; and differentially etching the metal layer relative to the other material by exposing the substrate to a controlled gas-phase environment containing an anhydrous halogen compound.

Abstract: Aspects of the disclosure provide a semiconductor apparatus that comprises a first field-effect transistor (FET) formed on a substrate and comprising a first gate, a second FET stacked on the first FET along a direction substantially perpendicular to the substrate and comprising a second gate. The semiconductor apparatus also comprises a first routing track and a second routing track electrically isolated from the first routing track. Each of the first and second routing tracks is provided on a routing plane stacked on the second FET along said direction. The semiconductor apparatus also comprises a first conductive trace configured to conductively couple the first gate of the first FET to the first routing track, and a second conductive trace configured to conductively couple the second gate of the second FET to the second routing track.

Abstract: A semiconductor device includes: a substrate having a planar surface; a first gate-all-around field effect transistor (GAA-FET) provided on said substrate and comprising a first channel having an untrimmed volume of first channel material corresponding to a volume of the first channel material within a first stacked fin structure from which the first channel was formed; and a second GAA-FET provided on said substrate and comprising a second channel having a trimmed volume of second channel material which is less than said untrimmed volume of first channel material by a predetermined trim amount corresponding to a delay adjustment of the second GAA-FET relative to the first GAA-FET, wherein said first and second GAA FETs are electrically connected as complementary FETs.

Abstract: A method of manufacturing a semiconductor device includes: providing a substrate including a first stacked fin structure for forming a channel of a first gate-all-around (GAA) transistor, the first stacked fin structure including an initial volume of first channel material, and a second stacked fin structure for forming a channel of a second GAA transistor, the second stacked fin structure including an initial volume of second channel material; reducing said initial volume of the second channel material relative to the initial volume of first channel material by a predetermined amount corresponding to a delay of the first GAA transistor; and forming first and second GAA gate structures around said first channel material and said second channel material respectively.

Abstract: A method of manufacturing a semiconductor device includes: providing a substrate having a base fin structure thereon, the base fin structure including a first stacked portion for forming a channel of a first gate-all-around (GAA) transistor, the first stacked portion including a first channel material, a second stacked portion for forming a channel of a second GAA transistor, the second stacked portion including second channel material, and a sacrificial portion separating the first stack portion from the second stack portion, wherein the first channel material, the second channel material and the sacrificial material have different chemical compositions from each other; exposing the side of the base fin structure to an isotropic etch process which selectively etches one of the first channel material, the second channel material and the sacrificial material; and forming first and second GAA gate structures around said first channel material and said second channel material respectively.

Abstract: A method and system for the dry removal of a material on a microelectronic workpiece are described. The method includes receiving a workpiece having a surface exposing a target layer to be at least partially removed, placing the workpiece on a workpiece holder in a dry, non-plasma etch chamber, and selectively removing at least a portion of the target layer from the workpiece. The selective removal includes operating the dry, non-plasma etch chamber to perform the following: exposing the surface of the workpiece to a chemical environment at a first setpoint temperature in the range of 35 degrees C. to 100 degrees C. to chemically alter a surface region of the target layer, and then, elevating the temperature of the workpiece to a second setpoint temperature at or above 100 degrees C. to remove the chemically treated surface region of the target layer.

Abstract: A method and system for the dry removal of a material on a microelectronic workpiece are described. The method includes receiving a workpiece having a surface exposing a target layer to be at least partially removed, placing the workpiece on a workpiece holder in a dry, non-plasma etch chamber, and selectively removing at least a portion of the target layer from the workpiece. The selective removal includes operating the dry, non-plasma etch chamber to perform the following: exposing the surface of the workpiece to a chemical environment at a first setpoint temperature in the range of 35 degrees C. to 100 degrees C. to chemically alter a surface region of the target layer, and then, elevating the temperature of the workpiece to a second setpoint temperature at or above 100 degrees C. to remove the chemically treated surface region of the target layer.

Abstract: Embodiments of the invention provide a method for forming NFET, PFET, or NFET and PFET nanowire devices on a substrate. According to one embodiment, the method includes providing a film stack containing a Si layer, a SiGe layer, and a Ge layer positioned between the Si layer and the SiGe layer, and selectively removing the Ge layer by etching that is selective to the Si layer and the SiGe layer, thereby forming an opening between the Si layer and the SiGe layer. According to another embodiment, the method providing a film stack containing alternating Si and Ge layers, and selectively removing the Ge layers by etching that is selective to the Si layers. According to another embodiment, the method includes providing a film stack containing a plurality of alternating SiGe and Ge layers, and selectively removing the plurality of Ge layers by etching that is selective to the SiGe layers.

Abstract: A method for the dry removal of a material on a microelectronic workpiece is described. The method includes receiving a substrate having a working surface exposing a silicon-germanium alloy and at least one other material, the silicon-germanium alloy represented as SixGe1-x, wherein x is a real number ranging from 0 to 1; and selectively etching the silicon-germanium alloy relative to the other material by exposing the substrate to a controlled gas-phase environment containing an anhydrous halogen compound, such as a diatomic halogen or an interhalogen compound.

Abstract: Embodiments of the invention provide methods for selective deposition on different materials using a surface treatment. According to one embodiment, the method includes providing a substrate containing a first material layer having a first surface and a second material layer having a second surface, and performing a chemical oxide removal process that terminates that second surface with hydroxyl groups. The method further includes modifying the second surface by exposure to a process gas containing a hydrophobic functional group, the modifying substituting the hydroxyl groups on the second surface with the hydrophobic functional group, and selectively depositing a metal-containing layer on the first surface but not on the modified second surface by exposing the substrate to a deposition gas.

Abstract: A method of manufacturing a semiconductor device includes: providing a substrate having a base fin structure thereon, the base fin structure including a first stacked portion for forming a channel of a first gate-all-around (GAA) transistor, the first stacked portion including a first channel material, a second stacked portion for forming a channel of a second GAA transistor, the second stacked portion including second channel material, and a sacrificial portion separating the first stack portion from the second stack portion, wherein the first channel material, the second channel material and the sacrificial material have different chemical compositions from each other; exposing the side of the base fin structure to an isotropic etch process which selectively etches one of the first channel material, the second channel material and the sacrificial material; and forming first and second GAA gate structures around said first channel material and said second channel material respectively.

Abstract: A method of manufacturing a semiconductor device includes: providing a substrate including a first stacked fin structure for forming a channel of a first gate-all-around (GAA) transistor, the first stacked fin structure including an initial volume of first channel material, and a second stacked fin structure for forming a channel of a second GAA transistor, the second stacked fin structure including an initial volume of second channel material; reducing said initial volume of the second channel material relative to the initial volume of first channel material by a predetermined amount corresponding to a delay of the first GAA transistor; and forming first and second GAA gate structures around said first channel material and said second channel material respectively.