Abstract: This application discloses distributed forward error correction in hardware assisted verification platforms (300) including a hardware-assisted verification system (320) to emulate an electronic system (322) described by a circuit design (301). The hardware-assisted verification system (320) can implement forward error correction circuitry (324) to analyse a data packet (311) for use by the emulated electronic system (322) during functional verification operations of the circuit design (301), which can identify that the data packet includes one or more corrupted bits (321). The forward error correction circuitry (324) can transmit the corrupted data packet (321) to a computing system (330) implementing an error correction algorithm configured to perform error correction operations (332) on the corrupted data packet (321).

Abstract: Aspects of the disclosed technology relate to techniques of latency test in networking system-on-chip design verification. A hardware model of interface circuitry implemented in a reconfigurable hardware modeling device associates arrival time information with messages when the messages are delivered to a hardware model of a circuit design implemented in the reconfigurable hardware modeling device, and associates latency information with the messages when the messages are dispatched by the hardware model of the circuit design. The arrival time information of a particular message and the latency information are determined with respect to a model time reference provided in the reconfigurable hardware modeling device.

Abstract: Traffic-shaping information is associated with ingress transaction-level messages by a traffic generation device. The ingress transaction-level messages and the traffic-shaping information are then sent to a reconfigurable hardware modeling device. The ingress transaction-level messages are converted to ingress signal-level messages by a hardware model of interface circuitry implemented in the reconfigurable hardware modeling device. Based on the traffic-shaping information, the ingress signal-level messages are delivered to a hardware model of a circuit design implemented in the reconfigurable hardware modeling device.

Abstract: Aspects of the disclosed technology relate to techniques of latency test in networking system-on-chip design verification. A hardware model of interface circuitry implemented in a reconfigurable hardware modeling device associates arrival time information with messages when the messages are delivered to a hardware model of a circuit design implemented in the reconfigurable hardware modeling device, and associates latency information with the messages when the messages are dispatched by the hardware model of the circuit design. The arrival time information of a particular message and the latency information are determined with respect to a model time reference provided in the reconfigurable hardware modeling device.

Abstract: Traffic-shaping information is associated with ingress transaction-level messages by a traffic generation device. The ingress transaction-level messages and the traffic-shaping information are then sent to a reconfigurable hardware modeling device. The ingress transaction-level messages are converted to ingress signal-level messages by a hardware model of interface circuitry implemented in the reconfigurable hardware modeling device. Based on the traffic-shaping information, the ingress signal-level messages are delivered to a hardware model of a circuit design implemented in the reconfigurable hardware modeling device.