Patents by Inventor Sudhanva Gurumurthi

Sudhanva Gurumurthi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11409608
    Abstract: Providing host-based error detection capabilities in a remote execution device is disclosed. A remote execution device performs a host-offloaded operation that modifies a block of data stored in memory. Metadata is generated locally for the modified of block of data such that the local metadata generation emulates host-based metadata generation. Stored metadata for the block of data is updated with the locally generated metadata for the modified portion of the block of data. When the host performs an integrity check on the modified block of data using the updated metadata, the host does not distinguish between metadata generated by the host and metadata generated in the remote execution device.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: August 9, 2022
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Shrikanth Ganapathy, Ross V. La Fetra, John Kalamatianos, Sudhanva Gurumurthi, Shaizeen Aga, Vilas Sridharan, Michael Ignatowski, Nuwan Jayasena
  • Publication number: 20220206901
    Abstract: Providing host-based error detection capabilities in a remote execution device is disclosed. A remote execution device performs a host-offloaded operation that modifies a block of data stored in memory. Metadata is generated locally for the modified of block of data such that the local metadata generation emulates host-based metadata generation. Stored metadata for the block of data is updated with the locally generated metadata for the modified portion of the block of data. When the host performs an integrity check on the modified block of data using the updated metadata, the host does not distinguish between metadata generated by the host and metadata generated in the remote execution device.
    Type: Application
    Filed: December 29, 2020
    Publication date: June 30, 2022
    Inventors: SHRIKANTH GANAPATHY, ROSS V. LA FETRA, JOHN KALAMATIANOS, SUDHANVA GURUMURTHI, SHAIZEEN AGA, VILAS SRIDHARAN, MICHAEL IGNATOWSKI, NUWAN JAYASENA
  • Publication number: 20220206899
    Abstract: Methods and processing devices are provided for error protection to support instruction replay for executing idempotent instructions at a processing in memory PIM device. The processing apparatus includes a PIM device configured to execute an idempotent instruction. The processing apparatus also includes a processor, in communication with the PIM device, configured to issue the idempotent instruction to the PIM device for execution at the PIM device and reissue the idempotent instruction to the PIM device when one of execution of the idempotent instruction at the PIM device results in an error and a predetermined latency period expires from when the idempotent instruction is issued.
    Type: Application
    Filed: December 24, 2020
    Publication date: June 30, 2022
    Applicant: Advanced Micro Devices, Inc.
    Inventors: John Kalamatianos, Nuwan Jayasena, Sudhanva Gurumurthi, Shaizeen Aga, Shrikanth Ganapathy
  • Publication number: 20220197827
    Abstract: A method and system for memory attack mitigation in a memory device includes receiving, at a memory controller, an allocation of a page in memory. One or more device controllers detects an aggressor-victim set within the memory. Based upon the detection, an address of the allocated page is identified for further action.
    Type: Application
    Filed: December 17, 2020
    Publication date: June 23, 2022
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Sudhanva Gurumurthi, Vilas K. Sridharan
  • Publication number: 20220129345
    Abstract: Error handling for resilient software includes: receiving data indicating a region of resilient memory; detecting an error associated with a region of memory; and preventing raising an exception for the error in response to the region of memory falling within the region of resilient memory by preventing the region of memory as being identified as including the error.
    Type: Application
    Filed: January 10, 2022
    Publication date: April 28, 2022
    Inventors: SUDHANVA GURUMURTHI, VILAS SRIDHARAN
  • Publication number: 20220100606
    Abstract: A memory module includes one or more programmable ECC engines that may be programed by a host processing element with a particular ECC implementation. As used herein, the term “ECC implementation” refers to ECC functionality for performing error detection and subsequent processing, for example using the results of the error detection to perform error correction and to encode corrupted data that cannot be corrected, etc. The approach allows an SoC designer or company to program and reprogram ECC engines in memory modules in a secure manner without having to disclose the particular ECC implementations used by the ECC engines to memory vendors or third parties.
    Type: Application
    Filed: September 25, 2020
    Publication date: March 31, 2022
    Inventors: SUDHANVA GURUMURTHI, VILAS SRIDHARAN, SHAIZEEN AGA, NUWAN JAYASENA, MICHAEL IGNATOWSKI, SHRIKANTH GANAPATHY, JOHN KALAMATIANOS
  • Patent number: 11221902
    Abstract: Error handling for resilient software includes: receiving data indicating a region of resilient memory; detecting an error associated with a region of memory; and preventing raising an exception for the error in response to the region of memory falling within the region of resilient memory by preventing the region of memory as being identified as including the error.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: January 11, 2022
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Sudhanva Gurumurthi, Vilas Sridharan
  • Publication number: 20210342241
    Abstract: A method and apparatus for predicting and managing a device failure includes responsive to a predicted failure of a memory device, the predicted failure based on sensor data associated with the memory device, determining a further action for the memory device.
    Type: Application
    Filed: April 29, 2020
    Publication date: November 4, 2021
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Sudhanva Gurumurthi, Vilas K. Sridharan
  • Publication number: 20210182139
    Abstract: Error handling for resilient software includes: receiving data indicating a region of resilient memory; detecting an error associated with a region of memory; and preventing raising an exception for the error in response to the region of memory falling within the region of resilient memory by preventing the region of memory as being identified as including the error.
    Type: Application
    Filed: December 16, 2019
    Publication date: June 17, 2021
    Inventors: SUDHANVA GURUMURTHI, VILAS SRIDHARAN
  • Publication number: 20210182135
    Abstract: A method and apparatus for predicting and managing a fault in memory includes detecting an error in data. The error is compared to one or more stored errors in a filter, and based upon the comparison, the error is predicted as a transient error or a permanent error for further action.
    Type: Application
    Filed: December 17, 2019
    Publication date: June 17, 2021
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Sudhanva Gurumurthi, Vilas K. Sridharan
  • Publication number: 20210117269
    Abstract: A system and method for protecting memory instructions against faults are described. The system and method include converting the slave instructions to dummy operations, modifying memory arbiter to issue up to N master and N slave global/shared memory instructions per cycle, sending master memory requests to memory system, using slave requests for error checking, entering master requests to the GM/LM FIFO, storing slave requests in a register, and comparing the entered master requests with the stored slave requests.
    Type: Application
    Filed: December 7, 2020
    Publication date: April 22, 2021
    Applicant: Advanced Micro Devices, Inc.
    Inventors: John Kalamatianos, Michael Mantor, Sudhanva Gurumurthi
  • Publication number: 20210089398
    Abstract: Selecting an error correction code type for a memory device includes: selecting, by the memory device in dependence upon predefined selection criteria, one of a plurality of error correction code types and carrying out memory access requests utilizing the selected error correction code type.
    Type: Application
    Filed: September 25, 2019
    Publication date: March 25, 2021
    Inventors: SUDHANVA GURUMURTHI, VILAS SRIDHARAN
  • Publication number: 20210049446
    Abstract: A system comprising an electronic device that includes a processor is described. During operation, the processor acquires a full version of a neural network, the neural network including internal elements for processing instances of input image data having a set of color channels. The processor then generates, from the neural network, a set of sub-networks, each sub-network being a separate copy of the neural network with the internal elements for processing at least one of the color channels in instances of input image data removed, so that each sub-network is configured for processing a different set of one or more color channels in instances of input image data. The processor next provides the sub-networks for processing instances of input image data—and may itself use the sub-networks for processing instances of input image data.
    Type: Application
    Filed: August 12, 2019
    Publication date: February 18, 2021
    Inventors: Sudhanva Gurumurthi, Abhinav Vishnu
  • Patent number: 10860418
    Abstract: A system and method for protecting memory instructions against faults are described. The system and method include converting the slave instructions to dummy operations, modifying memory arbiter to issue up to N master and N slave global/shared memory instructions per cycle, sending master memory requests to memory system, using slave requests for error checking, entering master requests to the GM/LM FIFO, storing slave requests in a register, and comparing the entered master requests with the stored slave requests.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: December 8, 2020
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: John Kalamatianos, Michael Mantor, Sudhanva Gurumurthi
  • Publication number: 20200380063
    Abstract: Techniques for performing in-memory matrix multiplication, taking into account temperature variations in the memory, are disclosed. In one example, the matrix multiplication memory uses ohmic multiplication and current summing to perform the dot products involved in matrix multiplication. One downside to this analog form of multiplication is that temperature affects the accuracy of the results. Thus techniques are provided herein to compensate for the effects of temperature increases on the accuracy of in-memory matrix multiplications. According to the techniques, portions of input matrices are classified as effective or ineffective. Effective portions are mapped to low temperature regions of the in-memory matrix multiplier and ineffective portions are mapped to high temperature regions of the in-memory matrix multiplier. The matrix multiplication is then performed.
    Type: Application
    Filed: May 31, 2019
    Publication date: December 3, 2020
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Majed Valad Beigi, Amin Farmahini-Farahani, Sudhanva Gurumurthi
  • Publication number: 20200272726
    Abstract: An apparatus includes one or more processors that are configured to determine a pixel-by-pixel bounds for a perturbed image, generate an adversarial example using an adversarial example generation technique, and modify the adversarial example to generate the perturbed image based on the pixel-by-pixel bounds. When an initial perturbed image does not reside within the pixel-by-pixel bounds, the one or more processors adjust the initial perturbed image to generate the perturbed image by a Weber-Fechner based adversarial perturbation to reside within the pixel-by-pixel bounds. The one or more processors provide the perturbed image to a computing device in an image-based Completely Automated Public Turing Test to tell Computers and Humans Apart (CAPTCHA).
    Type: Application
    Filed: December 10, 2019
    Publication date: August 27, 2020
    Inventors: Scott MOE, Nicholas Penha MALAYA, Sudhanva GURUMURTHI, Naman MAHESHWARI
  • Publication number: 20200151572
    Abstract: A system is described that performs training operations for a neural network, the system including an analog circuit element functional block with an array of analog circuit elements, and a controller. The controller monitors error values computed using an output from each of one or more initial iterations of a neural network training operation, the one or more initial iterations being performed using neural network data acquired from the memory. When one or more error values are less than a threshold, the controller uses the neural network data from the memory to configure the analog circuit element functional block to perform remaining iterations of the neural network training operation. The controller then causes the analog circuit element functional block to perform the remaining iterations.
    Type: Application
    Filed: November 14, 2018
    Publication date: May 14, 2020
    Inventor: Sudhanva Gurumurthi
  • Publication number: 20200042859
    Abstract: Systems, apparatuses, and methods for managing buffers in a neural network implementation with heterogeneous memory are disclosed. A system includes a neural network coupled to a first memory and a second memory. The first memory is a relatively low-capacity, high-bandwidth memory while the second memory is a relatively high-capacity, low-bandwidth memory. During a forward propagation pass of the neural network, a run-time manager monitors the usage of the buffers for the various layers of the neural network. During a backward propagation pass of the neural network, the run-time manager determines how to move the buffers between the first and second memories based on the monitored buffer usage during the forward propagation pass. As a result, the run-time manager is able to reduce memory access latency for the layers of the neural network during the backward propagation pass.
    Type: Application
    Filed: November 19, 2018
    Publication date: February 6, 2020
    Inventors: Georgios Mappouras, Amin Farmahini-Farahani, Sudhanva Gurumurthi, Abhinav Vishnu, Gabriel H. Loh
  • Patent number: 10496561
    Abstract: Systems, apparatuses, and methods for routing traffic through vertically stacked memory are disclosed. A computing system includes a host processor die and multiple vertically stacked memory dies. The host processor die generates memory access requests for the data stored in the multiple memory array banks in the memory dies. At least one memory die uses an on-die network switch with a programmable routing table for routing packets corresponding to the generated memory requests. Routes use both vertical hops and horizontal hops to reach the target memory array bank and to avoid any congested or failed resources along the route. The vertically stacked memory dies use through silicon via interconnects and at least one via does not traverse through all of the memory dies. Accordingly, the host processor die does not have a direct connection to one or more of the multiple memory dies.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: December 3, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: David A. Roberts, Sudhanva Gurumurthi
  • Publication number: 20190235953
    Abstract: A system and method for protecting memory instructions against faults are described. The system and method include converting the slave instructions to dummy operations, modifying memory arbiter to issue up to N master and N slave global/shared memory instructions per cycle, sending master memory requests to memory system, using slave requests for error checking, entering master requests to the GM/LM FIFO, storing slave requests in a register, and comparing the entered master requests with the stored slave requests.
    Type: Application
    Filed: April 8, 2019
    Publication date: August 1, 2019
    Applicant: Advanced Micro Devices, Inc.
    Inventors: John Kalamatianos, Michael Mantor, Sudhanva Gurumurthi