Patents by Inventor Sugako Ohtani
Sugako Ohtani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11714639Abstract: A data processing device has an instruction decoder, a control logic unit, and ALU. The instruction decoder decodes instruction codes of an arithmetic instruction. The control logic unit detects the effective data width of operation data to be processed according to the decode result from the instruction decoder and determines the number of cycles for the instruction execution corresponding to the effective, data width. The ALU executes the instruction with the number of cycles of the instruction execution determined by the control logic unit.Type: GrantFiled: December 29, 2021Date of Patent: August 1, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Sugako Ohtani, Hiroyuki Kondo
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Publication number: 20220121442Abstract: A data processing device has an instruction decoder, a control logic unit, and ALU. The instruction decoder decodes instruction codes of an arithmetic instruction. The control logic unit detects the effective data width of operation data to be processed according to the decode result from the instruction decoder and determines the number of cycles for the instruction execution corresponding to the effective, data width. The ALU executes the instruction with the number of cycles of the instruction execution determined by the control logic unit.Type: ApplicationFiled: December 29, 2021Publication date: April 21, 2022Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Sugako OHTANI, Hiroyuki KONDO
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Patent number: 11231925Abstract: A data processing device has an instruction decoder, a control logic unit, and ALU. The instruction decoder decodes instruction codes of an arithmetic instruction. The control logic unit detects the effective data width of operation data to be processed according to the decode result from the instruction decoder and determines the number of cycles for the instruction execution corresponding to the effective, data width. The ALU executes the instruction with the number of cycles of the instruction execution determined by the control logic unit.Type: GrantFiled: January 21, 2020Date of Patent: January 25, 2022Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Sugako Ohtani, Hiroyuki Kondo
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Publication number: 20200159528Abstract: A data processing device has an instruction decoder, a control logic unit, and ALU. The instruction decoder decodes instruction codes of an arithmetic instruction. The control logic unit detects the effective data width of operation data to be processed according to the decode result from the instruction decoder and determines the number of cycles for the instruction execution corresponding to the effective, data width. The ALU executes the instruction with the number of cycles of the instruction execution determined by the control logic unit.Type: ApplicationFiled: January 21, 2020Publication date: May 21, 2020Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Sugako OHTANI, Hiroyuki KONDO
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Patent number: 10552149Abstract: A data processing device has an instruction decoder, a control logic unit, and ALU. The instruction decoder decodes instruction codes of an arithmetic instruction. The control logic unit detects the effective data width of operation data to be processed according to the decode result from the instruction decoder and determines the number of cycles for the instruction execution corresponding to the effective, data width. The ALU executes the instruction with the number of cycles of the instruction execution determined by the control logic unit.Type: GrantFiled: May 23, 2018Date of Patent: February 4, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Sugako Ohtani, Hiroyuki Kondo
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Publication number: 20180267797Abstract: A data processing device has an instruction decoder, a control logic unit, and ALU. The instruction decoder decodes instruction codes of an arithmetic instruction. The control logic unit detects the effective data width of operation data to be processed according to the decode result from the instruction decoder and determines the number of cycles for the instruction execution corresponding to the effective, data width. The ALU executes the instruction with the number of cycles of the instruction execution determined by the control logic unit.Type: ApplicationFiled: May 23, 2018Publication date: September 20, 2018Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Sugako OHTANI, Hiroyuki KONDO
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Patent number: 10001991Abstract: A data processing device has an instruction decoder, a control logic unit, and ALU. The instruction decoder decodes instruction codes of an arithmetic instruction. The control logic unit detects the effective data width of operation data to be processed according to the decode result from the instruction decoder and determines the number of cycles for the instruction execution corresponding to the effective, data width. The ALU executes the instruction with the number of cycles of the instruction execution determined by the control logic unit.Type: GrantFiled: February 4, 2016Date of Patent: June 19, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Sugako Ohtani, Hiroyuki Kondo
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Publication number: 20160154646Abstract: A data processing device has an instruction decoder, a control logic unit, and ALU. The instruction decoder decodes instruction codes of an arithmetic instruction. The control logic unit detects the effective data width of operation data to be processed according to the decode result from the instruction decoder and determines the number of cycles for the instruction execution corresponding to the effective, data width. The ALU executes the instruction with the number of cycles of the instruction execution determined by the control logic unit.Type: ApplicationFiled: February 4, 2016Publication date: June 2, 2016Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Sugako OHTANI, Hiroyuki KONDO
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Patent number: 9280341Abstract: A data processing device has an instruction decoder, a control logic unit, and ALU. The instruction decoder decodes instruction codes of an arithmetic instruction. The control logic unit detects the effective data width of operation data to be processed according to the decode result from the instruction decoder and determines the number of cycles for the instruction execution corresponding to the effective, data width. The ALU executes the instruction with the number of cycles of the instruction execution determined by the control logic unit.Type: GrantFiled: December 31, 2013Date of Patent: March 8, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Sugako Ohtani, Hiroyuki Kondo
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Publication number: 20140115303Abstract: A data processing device has an instruction decoder, a control logic unit, and ALU. The instruction decoder decodes instruction codes of an arithmetic instruction. The control logic unit detects the effective data width of operation data to be processed according to the decode result from the instruction decoder and determines the number of cycles for the instruction execution corresponding to the effective, data width. The ALU executes the instruction with the number of cycles of the instruction execution determined by the control logic unit.Type: ApplicationFiled: December 31, 2013Publication date: April 24, 2014Applicant: Renesas Electronics CorporationInventors: Sugako OHTANI, Hiroyuki KONDO
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Patent number: 8627046Abstract: A data processing device has an instruction decoder, a control logic unit, and ALU. The instruction decoder decodes instruction codes of an arithmetic instruction. The control logic unit detects the effective data width of operation data to be processed according to the decode result from the instruction decoder and determines the number of cycles for the instruction execution corresponding to the effective, data width. The ALU executes the instruction with the number of cycles of the instruction execution determined by the control logic unit.Type: GrantFiled: May 23, 2011Date of Patent: January 7, 2014Assignee: Renesas Electronics CorporationInventors: Sugako Ohtani, Hiroyuki Kondo
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Publication number: 20110238958Abstract: A data processing device has an instruction decoder, a control logic unit, and ALU. The instruction decoder decodes instruction codes of an arithmetic instruction. The control logic unit detects the effective data width of operation data to be processed according to the decode result from the instruction decoder and determines the number of cycles for the instruction execution corresponding to the effective, data width. The ALU executes the instruction with the number of cycles of the instruction execution determined by the control logic unit.Type: ApplicationFiled: May 23, 2011Publication date: September 29, 2011Applicant: Renesas Electronics CorporationInventors: Sugako OHTANI, Hiroyuki Kondo
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Patent number: 7971037Abstract: A data processing device has an instruction decoder (1), a control logic unit (3), and ALU (4). The instruction decoder (1) decodes instruction codes of an arithmetic instruction. The control logic unit (3) detects the effective data width of operation data to be processed according to the decode result from the instruction decoder (1) and determines the number of cycles for the instruction execution corresponding to the effective data width. The ALU (4) executes the instruction with the number of cycles of the instruction execution determined by the control logic unit (3).Type: GrantFiled: May 26, 2009Date of Patent: June 28, 2011Assignee: Renesas Electronics CorporationInventors: Sugako Ohtani, Hiroyuki Kondo
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Publication number: 20090235058Abstract: A data processing device has an instruction decoder (1), a control logic unit (3), and ALU (4). The instruction decoder (1) decodes instruction codes of an arithmetic instruction. The control logic unit (3) detects the effective data width of operation data to be processed according to the decode result from the instruction decoder (1) and determines the number of cycles for the instruction execution corresponding to the effective data width. The ALU (4) executes the instruction with the number of cycles of the instruction execution determined by the control logic unit (3).Type: ApplicationFiled: May 26, 2009Publication date: September 17, 2009Applicant: Renesas Technology CorporationInventors: Sugako Ohtani, Hiroyuki Kondo
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Patent number: 7555635Abstract: A data processing device has an instruction decoder (1), a control logic unit (3), and ALU (4). The instruction decoder (1) decodes instruction codes of an arithmetic instruction. The control logic unit (3) detects the effective data width of operation data to be processed according to the decode result from the instruction decoder (1) and determines the number of cycles for the instruction execution corresponding to the effective data width. The ALU (4) executes the instruction with the number of cycles of the instruction execution determined by the control logic unit (3).Type: GrantFiled: July 26, 2007Date of Patent: June 30, 2009Assignee: Renesas Technology Corp.Inventors: Sugako Ohtani, Hiroyuki Kondo
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Patent number: 7337302Abstract: A data processing device has an instruction decoder (1), a control logic unit (3), and ALU (4). The instruction decoder (1) decodes instruction codes of an arithmetic instruction. The control logic unit (3) detects the effective data width of operation data to be processed according to the decode result from the instruction decoder (1) and determines the number of cycles for the instruction execution corresponding to the effective data width. The ALU (4) executes the instruction with the number of cycles of the instruction execution determined by the control logic unit (3).Type: GrantFiled: September 5, 2003Date of Patent: February 26, 2008Assignee: Renesas Technology Corp.Inventors: Sugako Ohtani, Hiroyuki Kondo
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Publication number: 20070271443Abstract: A data processing device has an instruction decoder (1), a control logic unit (3), and ALU (4). The instruction decoder (1) decodes instruction codes of an arithmetic instruction. The control logic unit (3) detects the effective data width of operation data to be processed according to the decode result from the instruction decoder (1) and determines the number of cycles for the instruction execution corresponding to the effective data width. The ALU (4) executes the instruction with the number of cycles of the instruction execution determined by the control logic unit (3).Type: ApplicationFiled: July 26, 2007Publication date: November 22, 2007Inventors: Sugako Ohtani, Hiroyuki Kondo
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Publication number: 20040049659Abstract: A data processing device has an instruction decoder (1), a control logic unit (3), and ALU (4). The instruction decoder (1) decodes instruction codes of an arithmetic instruction. The control logic unit (3) detects the effective data width of operation data to be processed according to the decode result from the instruction decoder (1) and determines the number of cycles for the instruction execution corresponding to the effective data width. The ALU (4) executes the instruction with the number of cycles of the instruction execution determined by the control logic unit (3).Type: ApplicationFiled: September 5, 2003Publication date: March 11, 2004Applicant: RENESAS TECHNOLOGY CORPORATIONInventors: Sugako Ohtani, Hiroyuki Kondo