Abstract: A semiconductor device comprising a first active pattern including a first lower pattern, and a plurality of first sheet patterns, a plurality of first gate structures on the first lower pattern, a second active pattern including a second lower pattern and a plurality of second sheet patterns, a plurality of second gate structures on the second lower pattern, a first source/drain recess between adjacent first gate structures, a second source/drain recess between adjacent second gate structures, first and second source/drain patterns in the first and second source/drain recesses, respectively, wherein a depth from an upper surface of the first lower pattern to a lowermost part of the first source/drain pattern is smaller than a depth from an upper surface of the second lower pattern to a lowermost part of the second source/drain pattern, and the first and second source/drain patterns include impurities of same conductive type.

Abstract: There is provided a semiconductor device capable of improving the performance and reliability of a device. The semiconductor device comprising an active pattern including, a lower pattern extending in a first direction, and a plurality of sheet patterns spaced apart from the lower pattern in a second direction perpendicular to the first direction, wherein the lower pattern includes a semiconductor material, a plurality of gate structures on the lower pattern and spaced apart from each other in the first direction, wherein each of the plurality of gate structures includes a gate electrode and a gate insulating film, a source/drain recess between adjacent ones of the gate structures, wherein a bottom of the source/drain recess is in the lower pattern, a bottom insulating liner in the bottom of the source/drain recess, and a source/drain pattern in the source/drain recess and on top of the bottom insulating liner.

Abstract: There is provided a semiconductor device capable of improving the performance and reliability of a device. The semiconductor device comprising, a first active pattern on a substrate, the first active pattern including a first lower pattern, which extends in a first direction, and first sheet patterns, which are on the first lower pattern, a second active pattern on the substrate, the second active pattern including a second lower pattern, which is spaced apart from the first lower pattern in a second direction and a second sheet patterns, which are on the second lower pattern, wherein the first lower pattern and the second lower pattern is separated by a fin trench.

Abstract: A method of manufacturing a semiconductor device includes forming a first fin-type pattern and a second fin-type pattern which are separated by a first trench between facing ends thereof, forming a first insulating layer filling the first trench, removing a portion of the first insulating layer to form a second trench on the first insulating layer, and forming a third trench by enlarging a width of the second trench.

Abstract: A method of fabricating a semiconductor device is provided. The method includes: forming mask patterns on a substrate, the mask patterns including a first mask fin pattern, a second mask fin pattern and a dummy mask pattern between the first mask fin pattern and the second mask fin pattern; forming a first fin pattern, a second fin pattern and a dummy fin pattern by etching the substrate using the mask patterns; and removing the dummy fin pattern, wherein the dummy mask pattern is wider than each of the first mask fin pattern and the second mask fin pattern.

Abstract: A method of fabricating a semiconductor device is provided. The method includes: forming mask patterns on a substrate, the mask patterns including a first mask fin pattern, a second mask fin pattern and a dummy mask pattern between the first mask fin pattern and the second mask fin pattern; forming a first fin pattern, a second fin pattern and a dummy fin pattern by etching the substrate using the mask patterns; and removing the dummy fin pattern, wherein the dummy mask pattern is wider than each of the first mask fin pattern and the second mask fin pattern.

Abstract: A method of manufacturing a semiconductor device includes forming a first fin-type pattern and a second fin-type pattern which are separated by a first trench between facing ends thereof, forming a first insulating layer filling the first trench, removing a portion of the first insulating layer to form a second trench on the first insulating layer, and forming a third trench by enlarging a width of the second trench.

Abstract: A method of manufacturing a semiconductor device includes forming a first fin-type pattern and a second fin-type pattern which are separated by a first trench between facing ends thereof, forming a first insulating layer filling the first trench, removing a portion of the first insulating layer to form a second trench on the first insulating layer, and forming a third trench by enlarging a width of the second trench.

Abstract: A method of fabricating a semiconductor device is provided. The method includes: forming mask patterns on a substrate, the mask patterns including a first mask fin pattern, a second mask fin pattern and a dummy mask pattern between the first mask fin pattern and the second mask fin pattern; forming a first fin pattern, a second fin pattern and a dummy fin pattern by etching the substrate using the mask patterns; and removing the dummy fin pattern, wherein the dummy mask pattern is wider than each of the first mask fin pattern and the second mask fin pattern.

Abstract: An integrated circuit device includes a fin-type active area protruding from a substrate; a plurality of liners sequentially covering lower side walls of the fin-type active area; a device isolation layer covering the lower side walls of the fin-type active area with the plurality of liners between the device isolation layer and the fin-type active area; and a gate insulating layer extending to cover a channel region of the fin-type active area, the plurality of liners, and the device isolation layer, and including protrusions located on portions of the gate insulating layer which cover the plurality of liners.

Abstract: A method of manufacturing a semiconductor device includes forming a first fin-type pattern and a second fin-type pattern which are separated by a first trench between facing ends thereof, forming a first insulating layer filling the first trench, removing a portion of the first insulating layer to form a second trench on the first insulating layer, and forming a third trench by enlarging a width of the second trench.

Abstract: An integrated circuit device includes a fin-type active area protruding from a substrate; a plurality of liners sequentially covering lower side walls of the fin-type active area; a device isolation layer covering the lower side walls of the fin-type active area with the plurality of liners between the device isolation layer and the fin-type active area; and a gate insulating layer extending to cover a channel region of the fin-type active area, the plurality of liners, and the device isolation layer, and including protrusions located on portions of the gate insulating layer which cover the plurality of liners.

Abstract: Provided is a semiconductor device and a fabricating method thereof. The semiconductor device includes a first trench having a first depth to define a fin, a second trench formed directly adjacent the first trench having a second depth that is greater than the first depth, a field insulation layer filling a portion of the first trench and a portion of the second trench, and a protrusion structure protruding from a bottom of the first trench and being lower than a surface of the field insulation layer.

Abstract: A method of manufacturing a semiconductor device includes forming a first fin-type pattern and a second fin-type pattern which are separated by a first trench between facing ends thereof, forming a first insulating layer filling the first trench, removing a portion of the first insulating layer to form a second trench on the first insulating layer, and forming a third trench by enlarging a width of the second trench.

Abstract: An integrated circuit device includes a fin-type active area protruding from a substrate; a plurality of liners sequentially covering lower side walls of the fin-type active area; a device isolation layer covering the lower side walls of the fin-type active area with the plurality of liners between the device isolation layer and the fin-type active area; and a gate insulating layer extending to cover a channel region of the fin-type active area, the plurality of liners, and the device isolation layer, and including protrusions located on portions of the gate insulating layer which cover the plurality of liners.

Abstract: Provided is a semiconductor device and a fabricating method thereof. The semiconductor device includes a first trench having a first depth to define a fin, a second trench formed directly adjacent the first trench having a second depth that is greater than the first depth, a field insulation layer filling a portion of the first trench and a portion of the second trench, and a protrusion structure protruding from a bottom of the first trench and being lower than a surface of the field insulation layer.

Abstract: Provided is a semiconductor device and a fabricating method thereof. The semiconductor device includes a first trench having a first depth to define a fin, a second trench formed directly adjacent the first trench having a second depth that is greater than the first depth, a field insulation layer filling a portion of the first trench and a portion of the second trench, and a protrusion structure protruding from a bottom of the first trench and being lower than a surface of the field insulation layer.

Abstract: An integrated circuit device includes a fin-type active area protruding from a substrate; a plurality of liners sequentially covering lower side walls of the fin-type active area; a device isolation layer covering the lower side walls of the fin-type active area with the plurality of liners between the device isolation layer and the fin-type active area; and a gate insulating layer extending to cover a channel region of the fin-type active area, the plurality of liners, and the device isolation layer, and including protrusions located on portions of the gate insulating layer which cover the plurality of liners.

Abstract: Integrated circuit devices are provided. The devices may include first and second fin-shaped channel regions protruding from a substrate, and the first and second fin-shaped channel regions may define a recess therebetween. The devices may also include an isolation layer in a lower portion of the recess. The isolation layer may include a first stress liner extending along a side of the first fin-shaped channel region, a second stress liner extending along a side of the second fin-shaped channel region and an insulation liner between the first stress liner and the side of the first fin-shaped channel region and between the second stress liner and the side of the second fin-shaped channel region. The devices may further include a gate insulation layer on surfaces of upper portions of the first and second fin-shaped channel regions and a gate electrode layer on the gate insulation layer.

Abstract: An integrated circuit device includes a fin-type active area protruding from a substrate; a plurality of liners sequentially covering lower side walls of the fin-type active area; a device isolation layer covering the lower side walls of the fin-type active area with the plurality of liners between the device isolation layer and the fin-type active area; and a gate insulating layer extending to cover a channel region of the fin-type active area, the plurality of liners, and the device isolation layer, and including protrusions located on portions of the gate insulating layer which cover the plurality of liners.