Patents by Inventor Suguru ARIKATA

Suguru ARIKATA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10938181
    Abstract: A vertical cavity surface emitting laser includes: an active layer including a quantum well structure including one or more well layers including a III-V compound semiconductor containing indium as a group III constituent element; an upper laminated region containing a carbon dopant; and a substrate for mounting a post including the active layer and the upper laminated region, in which the active layer is provided between the upper laminated region and the substrate, the quantum well structure has a carbon concentration of 2×1016 cm?3 or less, and the upper laminated region includes a pile-up layer of indium at a position away from the active layer.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: March 2, 2021
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Kei Fujii, Takamichi Sumitomo, Suguru Arikata
  • Patent number: 10714640
    Abstract: A semiconductor stacked body includes: a first semiconductor layer containing a group III-V compound semiconductor and being a layer whose conductivity type is a first conductivity type; a quantum-well light-receiving layer containing a group III-V compound semiconductor; a second semiconductor layer containing a group III-V compound semiconductor; and a third semiconductor layer containing a group III-V compound semiconductor and being a layer whose conductivity type is a second conductivity type. The first semiconductor layer, the quantum-well light-receiving layer, the second semiconductor layer, and the third semiconductor layer are stacked in this order. The concentration of an impurity that generates a carrier of the second conductivity type is 1×1014 cm?3 or more and 1×1017 cm?3 or less in the second semiconductor layer.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: July 14, 2020
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takuma Fuyuki, Suguru Arikata, Susumu Yoshimoto, Katsushi Akita
  • Patent number: 10594110
    Abstract: A vertical cavity surface emitting laser includes: a supporting base having a principal surface including III-V compound semiconductor containing gallium and arsenic as constituent elements; and a post disposed on the principal surface. The post has a lower spacer region including a III-V compound semiconductor containing gallium and arsenic as group-III elements, and an active layer having a quantum well structure disposed on the lower spacer region. The quantum well structure has a concentration of carbon in a range of 2×1016 cm?3 or more to 5×1016 cm?3 or less. The quantum well structure includes a well layer and a barrier layer. The well layer includes a III-V compound semiconductor containing indium as a group-III element, and the barrier layer includes a III-V compound semiconductor containing indium and aluminum as group-III elements. The lower spacer region is disposed between the supporting base and the active layer.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: March 17, 2020
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Kei Fujii, Toshiyuki Tanahashi, Takashi Ishizuka, Susumu Yoshimoto, Takamichi Sumitomo, Koji Nishizuka, Suguru Arikata
  • Publication number: 20200076161
    Abstract: A vertical cavity surface emitting laser includes: an active layer including a quantum well structure including one or more well layers including a III-V compound semiconductor containing indium as a group III constituent element; an upper laminated region containing a carbon dopant; and a substrate for mounting a post including the active layer and the upper laminated region, in which the active layer is provided between the upper laminated region and the substrate, the quantum well structure has a carbon concentration of 2×1016 cm?3 or less, and the upper laminated region includes a pile-up layer of indium at a position away from the active layer.
    Type: Application
    Filed: August 29, 2019
    Publication date: March 5, 2020
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Kei FUJII, Takamichi Sumitomo, Suguru Arikata
  • Publication number: 20200028328
    Abstract: A vertical cavity surface emitting laser includes an active layer having a quantum well structure, a first laminate for a first distributed Bragg reflector, and a first spacer region provided between the active layer and the first laminate. A barrier layer of the quantum well structure includes a first compound semiconductor containing aluminum as a group m constituent element. The first spacer region includes a second compound semiconductor having a larger aluminum composition than the first compound semiconductor. A concentration of first dopant in the first laminate is larger than a concentration of the first dopant in the first portion of the first spacer region. The concentration of the first dopant in the first portion of the first spacer region is larger than a concentration of the first dopant in the second portion of the first spacer region.
    Type: Application
    Filed: July 18, 2019
    Publication date: January 23, 2020
    Applicant: Sumitomo Electric Industries, LTD.
    Inventors: Suguru ARIKATA, Susumu YOSHIMOTO, Takamichi SUMITOMO, Kei FUJII
  • Patent number: 10326034
    Abstract: A semiconductor layer includes a first semiconductor layer containing a III-V group compound semiconductor and having a first conductivity type, a quantum-well structure containing a III-V group compound semiconductor, a second semiconductor layer containing a III-V group compound semiconductor, a third semiconductor layer containing a III-V group compound semiconductor, and a fourth semiconductor layer containing a III-V group compound semiconductor and having a second conductivity type different from the first conductivity type. The first semiconductor layer, the quantum-well structure, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are stacked in this order. The concentration of an impurity that generates carriers of the second conductivity type is lower in the third semiconductor layer than in the fourth semiconductor layer.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: June 18, 2019
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Suguru Arikata, Takuma Fuyuki, Susumu Yoshimoto, Takashi Kyono, Katsushi Akita
  • Publication number: 20190148914
    Abstract: A vertical cavity surface emitting laser includes: a supporting base having a principal surface including III-V compound semiconductor containing gallium and arsenic as constituent elements; and a post disposed on the principal surface. The post has a lower spacer region including a III-V compound semiconductor containing gallium and arsenic as group-III elements, and an active layer having a quantum well structure disposed on the lower spacer region. The quantum well structure has a concentration of carbon in a range of 2×1016 cm?3 or more to 5×1016 cm?3 or less. The quantum well structure includes a well layer and a barrier layer. The well layer includes a III-V compound semiconductor containing indium as a group-III element, and the barrier layer includes a III-V compound semiconductor containing indium and aluminum as group-III elements. The lower spacer region is disposed between the supporting base and the active layer.
    Type: Application
    Filed: November 13, 2018
    Publication date: May 16, 2019
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Kei Fujii, Toshiyuki Tanahashi, Takashi Ishizuka, Susumu Yoshimoto, Takamichi Sumitomo, Koji Nishizuka, Suguru Arikata
  • Publication number: 20190044306
    Abstract: A vertical cavity surface emitting laser includes: an active layer; a first laminate for a first distributed Bragg reflector; and a first intermediate layer disposed between the active layer and the first laminate. The first intermediate layer has first and second portions. The first laminate, the first and second portions of the first intermediate layer, and the active layer are arranged along a direction of a first axis. The first laminate and the first portion of the first intermediate layer each include a first dopant. The active layer has a first-dopant concentration of less than 1×1016 cm?3. The first portion of the first intermediate layer has a first-dopant concentration smaller than that of the first laminate. The second portion of the first intermediate layer has a first-dopant concentration smaller than that of the first portion of the first intermediate layer.
    Type: Application
    Filed: July 30, 2018
    Publication date: February 7, 2019
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Toshiyuki TANAHASHI, Takashi ISHIZUKA, Susumu YOSHIMOTO, Takamichi SUMITOMO, Koji NISHIZUKA, Kei FUJI, Suguru ARIKATA
  • Publication number: 20190044010
    Abstract: A semiconductor layer includes a first semiconductor layer containing a III-V group compound semiconductor and having a first conductivity type, a quantum-well structure containing a III-V group compound semiconductor, a second semiconductor layer containing a III-V group compound semiconductor, a third semiconductor layer containing a III-V group compound semiconductor, and a fourth semiconductor layer containing a III-V group compound semiconductor and having a second conductivity type different from the first conductivity type. The first semiconductor layer, the quantum-well structure, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are stacked in this order. The concentration of an impurity that generates carriers of the second conductivity type is lower in the third semiconductor layer than in the fourth semiconductor layer.
    Type: Application
    Filed: January 24, 2017
    Publication date: February 7, 2019
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Suguru ARIKATA, Takuma FUYUKI, Susumu YOSHIMOTO, Takashi KYONO, Katsushi AKITA
  • Publication number: 20190035954
    Abstract: A semiconductor stacked body includes: a first semiconductor layer containing a group III-V compound semiconductor and being a layer whose conductivity type is a first conductivity type; a quantum-well light-receiving layer containing a group III-V compound semiconductor; a second semiconductor layer containing a group III-V compound semiconductor; and a third semiconductor layer containing a group III-V compound semiconductor and being a layer whose conductivity type is a second conductivity type. The first semiconductor layer, the quantum-well light-receiving layer, the second semiconductor layer, and the third semiconductor layer are stacked in this order. The concentration of an impurity that generates a carrier of the second conductivity type is 1×1014 cm?3 or more and 1×1017 cm?3 or less in the second semiconductor layer.
    Type: Application
    Filed: January 24, 2017
    Publication date: January 31, 2019
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takuma FUYUKI, Suguru ARIKATA, Susumu YOSHIMOTO, Katsushi AKITA
  • Patent number: 10158035
    Abstract: A semiconductor stack includes a first-conductivity-type layer of a first conductivity type, the first-conductivity-type layer being formed of a III-V compound semiconductor; a quantum well light-receiving layer formed of a III-V compound semiconductor; and a second-conductivity-type layer of a second conductivity type different from the first conductivity type, the second-conductivity-type layer being formed of a III-V compound semiconductor. The first-conductivity-type layer, the quantum well light-receiving layer, and the second-conductivity-type layer are stacked in this order. The quantum well light-receiving layer has a thickness of 0.5 ?m or more. The quantum well light-receiving layer has a carrier concentration of 1×1016 cm?3 or less.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: December 18, 2018
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takuma Fuyuki, Suguru Arikata, Takashi Kyono, Yusuke Yoshizumi, Katsushi Akita
  • Publication number: 20180122971
    Abstract: A semiconductor stack includes a first-conductivity-type layer of a first conductivity type, the first-conductivity-type layer being formed of a III-V compound semiconductor; a quantum well light-receiving layer formed of a III-V compound semiconductor; and a second-conductivity-type layer of a second conductivity type different from the first conductivity type, the second-conductivity-type layer being formed of a III-V compound semiconductor. The first-conductivity-type layer, the quantum well light-receiving layer, and the second-conductivity-type layer are stacked in this order. The quantum well light-receiving layer has a thickness of 0.5 ?m or more. The quantum well light-receiving layer has a carrier concentration of 1×1016 cm?3 or less.
    Type: Application
    Filed: April 8, 2016
    Publication date: May 3, 2018
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takuma FUYUKI, Suguru ARIKATA, Takashi KYONO, Yusuke YOSHIZUMI, Katsushi AKITA
  • Patent number: 9929301
    Abstract: A semiconductor stack includes a substrate composed of a III-V group compound semiconductor, a buffer layer that is arranged on the substrate and that is composed of a III-V group compound semiconductor, and an active layer that is arranged on the buffer layer and that includes a layer composed of a III-V group compound semiconductor containing Sb as a group V element. A region of the buffer layer including a main surface of the buffer layer adjacent to the substrate includes a high-concentration region having a high total concentration of Si and C compared with another adjacent region.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: March 27, 2018
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takashi Kyono, Suguru Arikata, Katsushi Akita
  • Publication number: 20180062019
    Abstract: A semiconductor stack includes a substrate composed of a III-V group compound semiconductor, a buffer layer that is arranged on the substrate and that is composed of a III-V group compound semiconductor, and an active layer that is arranged on the buffer layer and that includes a layer composed of a III-V group compound semiconductor containing Sb as a group V element. A region of the buffer layer including a main surface of the buffer layer adjacent to the substrate includes a high-concentration region having a high total concentration of Si and C compared with another adjacent region.
    Type: Application
    Filed: January 12, 2016
    Publication date: March 1, 2018
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takashi KYONO, Suguru ARIKATA, Katsushi AKITA
  • Publication number: 20170294547
    Abstract: A semiconductor layered structure includes a base layer, a quantum well structure, and a contact layer. The base layer, the quantum well structure, and the contact layer are disposed so as to be stacked in this order. In the contact layer, a region including a first main surface that is a main surface on a quantum well structure side has a p-type impurity concentration lower than a p-type impurity concentration of a region including a second main surface that is a main surface opposite to the first main surface. A photodiode includes the semiconductor layered structure and an electrode formed on the semiconductor layered structure. A sensor includes the photodiode and a read-out circuit connected to the photodiode.
    Type: Application
    Filed: October 21, 2015
    Publication date: October 12, 2017
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Kaoru SHIBATA, Koji NISHIZUKA, Suguru ARIKATA, Takashi KYONO, Katsushi AKITA
  • Publication number: 20170040477
    Abstract: A semiconductor layered structure according to the present invention includes a substrate formed of a III-V compound semiconductor; and semiconductor layers disposed on the substrate and formed of III-V compound semiconductors. The substrate has a majority-carrier-generating impurity concentration of 1×1017 cm?3 or more and 2×1020 cm?3 or less, and the impurity has an activation ratio of 30% or more.
    Type: Application
    Filed: December 17, 2014
    Publication date: February 9, 2017
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Suguru Arikata, Takashi Kyono, Koji Nishizuka, Kaoru Shibata, Katsushi Akita
  • Patent number: 9281427
    Abstract: An infrared photodiode that is a semiconductor device includes a substrate, a buffer layer formed of GaSb, and an absorption layer including a multiple quantum well structure. The multiple quantum well structure includes a stack of unit structures each including a plurality of component layers. Each unit structure includes a first component layer formed of InAs1-aSba where the ratio a is 0 or more and 0.05 or less, a second component layer formed of GaSb, and a third component layer formed of InSbxAs1-x where the ratio x is more than 0 and less than 1. The third component layer is disposed so as to be in contact with one main surface of the second component layer. The other main surface of the second component layer is in contact with the first component layer within the unit structure. The third component layer has a thickness of 0.1 nm or more and 0.9 nm or less.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: March 8, 2016
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takashi Kyono, Suguru Arikata, Katsushi Akita
  • Publication number: 20150372174
    Abstract: An infrared photodiode that is a semiconductor device includes a substrate, a buffer layer formed of GaSb, and an absorption layer including a multiple quantum well structure. The multiple quantum well structure includes a stack of unit structures each including a plurality of component layers. Each unit structure includes a first component layer formed of InAs1-aSba where the ratio a is 0 or more and 0.05 or less, a second component layer formed of GaSb, and a third component layer formed of InSbxAs1-x where the ratio x is more than 0 and less than 1. The third component layer is disposed so as to be in contact with one main surface of the second component layer. The other main surface of the second component layer is in contact with the first component layer within the unit structure. The third component layer has a thickness of 0.1 nm or more and 0.9 nm or less.
    Type: Application
    Filed: June 22, 2015
    Publication date: December 24, 2015
    Inventors: Takashi KYONO, Suguru ARIKATA, Katsushi AKITA