Patents by Inventor Suguru Yamazaki

Suguru Yamazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11960010
    Abstract: A positioning terminal is provided and identifies, as appropriate, a satellite to be excluded, thereby improving positioning accuracy. A processor acquires a signal-to-noise ratio (SNR) and an angle of elevation for each satellite. The processor next identifies a satellite for which the SNR is less than a shielding SNR mask as a multipath satellite and selects the satellite to be excluded. The processor next generates positioning terminal positioning data using a positioning signal from satellites other than the satellite to be excluded. The processor next uses reference station positioning data and positioning terminal positioning data of the selected satellite to execute an RTK calculation.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: April 16, 2024
    Assignees: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD., NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Yasuhisa Yamazaki, Suguru Oguchi, Yoshihiro Iriyama, Mamoru Kanayama
  • Publication number: 20240119745
    Abstract: By an object recognition device, an object recognition method, or a non-transitory computer-readable storage medium storing an object recognition program, matching between a three-dimensional dynamic map representing a state of a mapping point group obtained by mapping of a target existing in an observation space and three-dimensional observation data representing a state of an observation point group observed in the observation space is performed, a candidate point of the mobile object is searched, and the mobile object is identified.
    Type: Application
    Filed: December 6, 2023
    Publication date: April 11, 2024
    Inventors: SUGURU YAMAZAKI, TOMOYUKI OISHI, MOTOKI TANAKA
  • Publication number: 20210284197
    Abstract: In an accident pattern determination apparatus including a storage storing attributes assigned to respective ones of a plurality of predefined traffic situations, an acquirer acquires, for each of vehicle-related accident cases, an accident pattern that is a combination of traffic situations in the accident case, from the plurality of predefined traffic situations. A determiner determines, for each accident pattern acquired by the acquirer, whether the accident pattern is an accident pattern of high accident risk or an accident pattern of low accident risk for specific vehicles, based on the accident patterns acquired for the respective accident cases and the attributes assigned to respective ones of the plurality of predefined traffic situations.
    Type: Application
    Filed: March 8, 2021
    Publication date: September 16, 2021
    Inventors: Masataka MORI, Kenji MUTO, Kazuhito TAKENAKA, Daisuke HIRANO, Suguru YAMAZAKI, Yoshinori TAKEUCHI, Shun SHIMIZU
  • Patent number: 7808470
    Abstract: An electro-optical device includes an X address decoder that selects one of plural X selection lines, a Y address decoder that selects one of plural Y selection lines, and plural pixel blocks. Each pixel block is provided with respect to an intersection of a corresponding X selection line and a corresponding Y selection lines. Each pixel block includes a pixel circuit and the pixel circuits corresponding to a column share a bit line and a complementary bit line. Each pixel circuit includes a memory circuit, a selection circuit, and a pixel electrode. The memory circuit includes plural transistors that become conductive between the bit line, the complementary bit line, and terminals of the memory circuit at the time of concurrent selection of an X selection line and a Y selection line corresponding to the pixel block to which the plural transistors belong.
    Type: Grant
    Filed: September 5, 2006
    Date of Patent: October 5, 2010
    Assignee: Epson Imaging Device Corporation
    Inventors: Yutaka Ozawa, Suguru Yamazaki
  • Publication number: 20070052657
    Abstract: The invention provides an electro-optical device that includes an X address decoder that selects one of a plurality of X selection lines, a Y address decoder that selects one of a plurality of Y selection lines, and a plurality of pixel blocks, each of the pixel blocks being provided with respect to an intersection of a corresponding one of the plurality of the X selection lines and a corresponding one of the plurality of the Y selection lines. Such an electro-optical device is further configured as follows. Each of the plurality of the pixel blocks includes at least one pixel circuit. The pixel circuits corresponding to a column share a bit line and a complementary bit line. Each of the pixel circuits includes a memory circuit, a selection circuit, and a pixel electrode.
    Type: Application
    Filed: September 5, 2006
    Publication date: March 8, 2007
    Applicant: Sanyo Epson Imaging Devices Corp.
    Inventors: Yutaka Ozawa, Suguru Yamazaki
  • Patent number: 6940482
    Abstract: The invention simplifies the configuration of a comparators circuit used in an electrooptic device or the like, in which gradation data is stored for each pixel, to realize lower power consumption, higher definition and multiple gradation. Transistors in which gradation data D0 to D2 are respectively supplied to the gate terminals, and transistors in which gradation signals P0 to P2 resulting from counting are respectively supplied to the gate terminals are connected to form a comparator circuit. When the gradation signals P0 to P2 are less than the results of reversal of the gradation data D0 to D2, the comparator circuit is placed into a nonconductive state, while when the gradation signals P0 to P2 are equal to the results of reversal of the gradation data D0 to D2, the comparator circuit is placed into a conductive state. As a result, a pulse signal PW can be produced according to the gradation data D0 to D2 to realize a gradation display in a sub-field driving system.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: September 6, 2005
    Assignee: Seiko Epson Corporation
    Inventors: Ryo Ishii, Suguru Yamazaki
  • Patent number: 6900788
    Abstract: In an electrooptical apparatus having a function allowing part of a display screen to be in a display state and allowing the other to be in a non-display state, for a non-display region, application voltages for scanning electrodes are fixed at non-selection voltages, and application voltages for signal electrodes are fixed at voltages similar to the case of a full-screen ON-display or a full-screen OFF-display at least in a predetermined period. Therefore, power consumption in the partial display state can be reduced.
    Type: Grant
    Filed: July 9, 2002
    Date of Patent: May 31, 2005
    Assignee: Seiko Epson Corporation
    Inventor: Suguru Yamazaki
  • Patent number: 6873319
    Abstract: The invention provides an electro-optical device capable of a high-quality and high-definition tone display, a driving method thereof, a driving circuit thereof, and electronic equipment using the same. With the invention, one field is divided into a plurality of sub-fields, such that each pixel is turned on or off in each of the sub-fields so that the proportion of the period during which each pixel is turned on to the period during which the associated pixel is turned off within the one field corresponds to the proportion according to the tone data. Further, when each pixel is turned on, either a first voltage which is higher than a constant reference voltage applied to a counter electrode or a second voltage which is lower than the reference voltage is applied to a pixel electrode of the associated pixel, and when the pixel is turned off, a voltage equal to the reference voltage is applied to the pixel electrode of the pixel.
    Type: Grant
    Filed: January 26, 2001
    Date of Patent: March 29, 2005
    Assignee: Seiko Epson Corporation
    Inventors: Akira Inoue, Akihiko Ito, Ryo Ishii, Suguru Yamazaki
  • Patent number: 6771240
    Abstract: It is to manage both the reduction of power consumption and the enhancement of quality of picture when a partial display operation is performed. A scanning line driving circuit 350 supplies each of scanning lines 312 in a display region with selection signals in a second half part of one horizontal scanning time period and with non-selection signals in the rest thereof by inverting the polarity every vertical scanning time period. Further, the scanning line driving circuit 350 supplies each of scanning lines 312 in a non-display region with non-selection signals by inverting the polarity every one or more vertical scanning time periods. A data line driving circuit 250 supplies each of data lines 212 with a signal representing a positive-side voltage level VDP and a signal representing a negative-side voltage level VDN in first and second half parts of a horizontal scanning time period, respectively, for a period of time of the same length in the case that a scanning line 312 in a display region is selected.
    Type: Grant
    Filed: December 15, 2000
    Date of Patent: August 3, 2004
    Assignee: Seiko Epson Corporation
    Inventors: Akira Inoue, Suguru Yamazaki
  • Patent number: 6633287
    Abstract: A power supply circuit is provided for supplying a scanning line selection voltage to an electro-optical device. The electro-optical device includes pixels disposed at intersections between a plurality of scanning lines and a plurality of data lines, a voltage generation circuit for generating a selection voltage having a positive polarity (or a negative polarity) with respect to the center voltage of voltages applied to the data lines, a capacitor for storing the selection voltage, and an inverter circuit for inverting the polarity of the voltage stored in the capacitor with respect to the median voltage, and outputting the resultant voltage as a selection voltage having a negative polarity (or a positive polarity if the selection voltage has a negative polarity).
    Type: Grant
    Filed: May 30, 2000
    Date of Patent: October 14, 2003
    Assignee: Seiko Epson Corporation
    Inventors: Satoshi Yatabe, Suguru Yamazaki, Katsunori Yamazaki
  • Patent number: 6522319
    Abstract: In an electrooptical apparatus having a function allowing part of a display screen to be in a display state and allowing the other to be in a non-display state, for a non-display region, application voltages for scanning electrodes are fixed at non-selection voltages, and application voltages for signal electrodes are fixed at voltages similar to the case of a full-screen ON-display or a full-screen OFF-display at least in a predetermined period; therefore, power consumption in the partial display state can be reduced.
    Type: Grant
    Filed: October 7, 1999
    Date of Patent: February 18, 2003
    Assignee: Seiko Epson Corporation
    Inventor: Suguru Yamazaki
  • Publication number: 20030030608
    Abstract: In accordance with the invention, signal electrode voltages are generated based on a plurality of scanning pattern sets. A storage circuit stores a display pattern and scanning patterns belonging to a first scanning pattern set PA in association with selection data Ds. A data control unit inverts display data d based on an inversion control signal CTL to generate converted display data d′. The inversion control signal CTL becomes active in association with each element at which the first scanning pattern set differs from a second scanning pattern set. First to third data registers generate a display pattern based on the converted display data d′.
    Type: Application
    Filed: August 6, 2002
    Publication date: February 13, 2003
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Takashi Kurumisawa, Akihiko Ito, Suguru Yamazaki
  • Publication number: 20030011552
    Abstract: To simplify the configuration of a comparator circuit used in an electrooptic device or the like, in which gradation data is stored for each pixel, to realize lower power consumption, higher definition and multiple gradation. Transistors 31 to 33 in which gradation data D0 to D2 are respectively supplied to the gate terminals, and transistors 41 to 43 in which gradation signals P0 to P2 resulting from counting are respectively supplied to the gate terminals are connected as shown in the drawings to form a comparator circuit 30. When the gradation signals P0 to P2 are less than the results of reversal of the gradation data D0 to D2, the comparator circuit 30 is put into a nonconductive state, while when the gradation signals P0 to P2 are equal to the results of reversal of the gradation data D0 to D2, the comparator circuit 30 is put into a conductive state. As a result, a pulse signal PW can be produced according to the gradation data D0 to D2 to realize a gradation display in a sub-field driving system.
    Type: Application
    Filed: June 27, 2002
    Publication date: January 16, 2003
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Ryo Ishii, Suguru Yamazaki
  • Publication number: 20020175887
    Abstract: In an electrooptical apparatus having a function allowing part of a display screen to be in a display state and allowing the other to be in a non-display state, for a non-display region, application voltages for scanning electrodes are fixed at non-selection voltages, and application voltages for signal electrodes are fixed at voltages similar to the case of a full-screen ON-display or a full-screen OFF-display at least in a predetermined period. Therefore, power consumption in the partial display state can be reduced.
    Type: Application
    Filed: July 9, 2002
    Publication date: November 28, 2002
    Inventor: Suguru Yamazaki
  • Publication number: 20020154104
    Abstract: In order to provide an electro-optical device capable of a high-quality and high-definition tone display, a driving method thereof, a driving circuit thereof, and electronic equipment using the electro-optical device, a driving method of an electro-optical device according to the present invention is characterized in that one field is divided into a plurality of sub-fields, such that each pixel is turned on or off in each of the sub-fields so that the proportion of the period during which each pixel is turned on to the period during which the associated pixel is turned off within the one field corresponds to the proportion according to the tone data, and when each pixel is turned on, either a first voltage which is higher than a constant reference voltage applied to a counter electrode or a second voltage which is lower than the reference voltage is applied to a pixel electrode of the associated pixel, and when the pixel is turned off, a voltage equal to the reference voltage is applied to the pixel electrode
    Type: Application
    Filed: October 2, 2001
    Publication date: October 24, 2002
    Inventors: Akira Inoue, Akihiko Ito, Ryo Ishii, Suguru Yamazaki
  • Publication number: 20020126107
    Abstract: It is to manage both the reduction of power consumption and the enhancement of quality of picture when a partial display operation is performed. A scanning line driving circuit 350 supplies each of scanning lines 312 in a display region with selection signals in a second half part of one horizontal scanning time period and with non-selection signals in the rest thereof by inverting the polarity every vertical scanning time period. Further, the scanning line driving circuit 350 supplies each of scanning lines 312 in a non-display region with non-selection signals by inverting the polarity every one or more vertical scanning time periods. A data line driving circuit 250 supplies each of data lines 212 with a signal representing a positive-side voltage level VDP and a signal representing a negative-side voltage level VDN in first and second half parts of a horizontal scanning time period, respectively, for a period of time of the same length in the case that a scanning line 312 in a display region is selected.
    Type: Application
    Filed: December 15, 2000
    Publication date: September 12, 2002
    Inventors: Akira Inoue, Suguru Yamazaki
  • Patent number: 6317122
    Abstract: A power circuit which supplies VH, V3, V2, VC, −V2, −V3, VL, etc., which are potentials for driving a liquid crystal, with the objective of reducing the power consumption of a liquid crystal display device. Input power potentials VCC and GND are used without modification as V3 and VC, and high-level potentials VH and VL are supplied by a charge pump circuit. The charge pump circuit such as a negative-direction sextuple boosting circuit 2 uses a pulsed clock signal LP to operate. The circuit also has means for adjusting boosting/dropping ratios. The provision of two pumping capacitors ensures that a charge pump operation is performed every horizontal scan period, improving the display uniformity. When the supply of VCC, etc., is stopped, residual charge due to VH and VL is released. VCC and GND are used both as liquid crystal drive source and as power voltages for the logic portions of the drivers.
    Type: Grant
    Filed: September 16, 1999
    Date of Patent: November 13, 2001
    Assignee: Seiko Epson Corporation
    Inventor: Suguru Yamazaki
  • Patent number: 5986649
    Abstract: A power circuit which supplies VH, V3, V2, VC, -V2, -V3, VL, etc., which are potentials for driving a liquid crystal, with the objective of reducing the power consumption of a liquid crystal display device. Input power potentials VCC and GND are used without modification as V3 and VC, and high-level potentials VH and VL are supplied by a charge pump circuit. The charge pump circuit such as a negative-direction sextuple boosting circuit 2 uses a pulsed clock signal LP to operate. The circuit also has means for adjusting boosting/dropping ratios. The provision of two pumping capacitors ensures that a charge pump operation is performed every horizontal scan period, improving the display uniformity. When the supply of VCC, etc., is stopped, residual charge due to VH and VL is released. VCC and GND are used both as liquid crystal drive source and as power voltages for the logic portions of the drivers.
    Type: Grant
    Filed: September 11, 1996
    Date of Patent: November 16, 1999
    Assignee: Seiko Epson Corporation
    Inventor: Suguru Yamazaki
  • Patent number: 4404624
    Abstract: A power circuit for an electronic timepiece having a liquid crystal display includes a voltage regulation circuit, a voltage reduction circuit and a voltage booster circuit. In normal operation the voltage reduction circuit operates to drive the timekeeping circuits and extend battery life. When battery voltage drops due to heavy load, such as an alarm or lamp, the voltage regulation circuit and booster circuits operate to drive the timekeeping circuits and liquid crystal display respectively. The same transistors operate in the voltage reduction and booster circuits.
    Type: Grant
    Filed: July 31, 1981
    Date of Patent: September 13, 1983
    Assignee: Kabushiki Kaisha Suwa Seikosha
    Inventor: Suguru Yamazaki
  • Patent number: 4358837
    Abstract: In an electronic timepiece the digital display of time functions is corrected by the manipulation of a multi-contact rotary switch. Rotation of the switch in one direction corrects one displayed function, e.g., hours and minutes, and rotation of the switch in the other direction corrects another displayed function, e.g., day and date. The rate of display correction is responsive to the rate of switch rotation. Rotational direction is electronically determined by detecting which contact in the rotary switch is the first to close. Rate of switch rotation is determined by measuring the time required in cyclic actuation of the rotary switch contacts.
    Type: Grant
    Filed: March 13, 1979
    Date of Patent: November 9, 1982
    Assignee: Kabushiki Kaisha Suwa Seikosha
    Inventors: Suguru Yamazaki, Tadamori Saito