Patents by Inventor Sujeet Ayyapureddi

Sujeet Ayyapureddi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230096291
    Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for bad row mode. The memory may prevent proper access operations (e.g., read operations) from being performed on a selected bad row of the memory as part of a bad row mode. For example, the memory may store a bad row address and when an access address matches the bad row address, may suppress one or more signals, change data read from the address, or combinations thereof. The bad row mode may be used to provide a positive control for post package repair (PPR) operations on the memory. A controller may enter the memory into bad row mode and then test the memory to determine if the selected bad row can be located and repaired via PPR.
    Type: Application
    Filed: September 29, 2021
    Publication date: March 30, 2023
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Jack Riley, Scott Smith, Christian Mohr, Gary Howe, Joshua Alzheimer, Yoshinori Fujiwara, Sujeet Ayyapureddi, Randall Rooney
  • Patent number: 11600314
    Abstract: Apparatuses, systems, and methods for sketch circuits for refresh binning. The rows of a memory may have different information retention times. The row addresses may be sorted into different bins based on these information retention times. In order to store information about which row addresses are associated with which bins a sketch circuit may be used. When an address is generated as part of a refresh operation, it may be used to generate a number of different hash values, which may be used to index entries in a storage structure. The entries may indicate which bin the address is associated with. Based on the binning information, the memory may refresh the address at different rates (e.g., by determining whether to provide the address as a refresh address or not).
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: March 7, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Sujeet Ayyapureddi, Donald M. Morgan
  • Patent number: 11579971
    Abstract: A memory performs a sequence of ECS operations to read a codeword, detect and correct any errors, and write the corrected codeword back to the memory array. An ECS circuit counts errors which are detected, and sets a value of one or more ECS registers in a mode register if the count exceeds a threshold filter at the end of the ECS cycle. The memory also includes a forced ECS readout circuit, which responsive to a command, for example from a controller, sets the value(s) in the ECS register(s).
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: February 14, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Sujeet Ayyapureddi
  • Patent number: 11568918
    Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for analog row access rate determination. Accesses to different row addresses may be tracked by storing one or more received addresses in a slice of stack. Each slice includes an accumulator circuit which provides a voltage based on charge on a capacitor. When a row address is received, it may be compared to the row addresses stored in the stack, and if there is a match, the charge on the capacitor in the associated accumulator circuit is increased. Each slice may also include a voltage to time (VtoT) circuit which may be used to identify the highest of the voltages provided by the accumulator circuits. The row address stored in the slide with the highest voltage may be refreshed.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: January 31, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Sujeet Ayyapureddi, Raghukiran Sreeramaneni
  • Patent number: 11562783
    Abstract: Apparatuses, systems, and methods for reset of row hammer detector circuits. A row hammer detector circuit includes a hash circuit configured to store a hash key and provide a first count value based on a hash between the hash key and a row address corresponding to a row of memory cells of a memory array. The row hammer detector circuit is configured to provide a match signal in response to the count value exceeding a threshold to cause a targeted refresh of a victim row adjacent the row of memory cells. In response to exit from a self-refresh mode, the hash circuit is configured to update the stored hash key with a new hash key.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: January 24, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Sujeet Ayyapureddi
  • Patent number: 11562784
    Abstract: Apparatuses, systems, and methods for voltage based random number generation. A memory may include a number of different voltages, which may be used to power various operations of the memory. During access operations to the memory, the voltage may vary, for example as word lines of the memory are accessed. The variability of the voltage may represent a source of randomness and unpredictability in the memory. A random number generator may provide a random number based on the voltage. For example, an analog to binary converter (ADC) may generate a binary number based on the voltage, and the random number may be based on the binary number.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: January 24, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Sujeet Ayyapureddi
  • Publication number: 20230015086
    Abstract: A memory performs a sequence of ECS operations to read a codeword, detect and correct any errors, and write the corrected codeword back to the memory array. An ECS circuit counts errors which are detected, and sets a value of one or more ECS registers in a mode register if the count exceeds a threshold filter at the end of the ECS cycle. The memory also includes a forced ECS readout circuit, which responsive to a command, for example from a controller, sets the value(s) in the ECS register(s).
    Type: Application
    Filed: July 14, 2021
    Publication date: January 19, 2023
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Sujeet Ayyapureddi
  • Publication number: 20230010619
    Abstract: Apparatuses, systems, and methods for dynamically allocated aggressor detection. A memory may include an aggressor address storage structure which tracks access patterns to row addresses and their associated bank addresses. These may be used to determine if a row and bank address received as part of an access operation are an aggressor row and bank address. The aggressor row address may be used to generate a refresh address for a bank identified by the aggressor bank address. Since the aggressor storage structure tracks both row and bank addresses, its storage space may be dynamically allocated between banks based on access patterns to those banks.
    Type: Application
    Filed: September 14, 2022
    Publication date: January 12, 2023
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Sujeet Ayyapureddi, Donald M. Morgan
  • Publication number: 20220408886
    Abstract: Apparatuses, systems, and methods for memory module data drives. A memory module includes a number of memory devices as well as module logic. Each memory device provides data by driving voltages along a data bus with a data bus driver of the memory device. An output driver, which is located on the module logic receives the voltages along the data bus and drives voltages of an external data terminal to output the data. The output driver may have a greater drive strength than the data bus driver.
    Type: Application
    Filed: August 29, 2022
    Publication date: December 29, 2022
    Inventors: Sujeet Ayyapureddi, Henry Michael Lubowe, Edison Tam King Miguel, Matthew Joseph Kane, Jr-Jay Jhang, Jens Mitchell Nielsen, Cédric Eric Jean-Edouard Bernard, Brian Dennis Paschke, Junyong Park, Mark Woodhiser Huang, Stephanie Lydia Renee Choplin
  • Publication number: 20220399902
    Abstract: Apparatuses, systems, and methods for multi-bit error detection. A memory device may store data bits and parity bits in a memory array. An error correction code (ECC) circuit may generate syndrome bits based on the data and parity bits and use the syndrome bits to correct up to a single bit error in the data and parity bits. A multi-bit error (MBE) detection circuit may detect an MBE in the data and parity based on at least one of the syndrome bits or the parity bits. For example, the MBE detection circuit may determine if the syndrome bits have a mapped or unmapped state and/or may compare the parity bits, data bits, and an additional parity bit to determine if there is an MBE. When an MBE is detected an MBE signal is activated. In some embodiments, an MBE flag may be set based on the MBE signal being active.
    Type: Application
    Filed: June 15, 2021
    Publication date: December 15, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Markus H. Geiger, Matthew A. Prather, Sujeet Ayyapureddi, C. Omar Benitez, Dennis Montierth
  • Publication number: 20220374168
    Abstract: Memory devices and systems with memory-initiated command insertion (and associated methods) are disclosed herein. In one embodiment, a memory device comprises a command insertion terminal configured to be operably connected to a memory controller. The memory device can (i) identify a condition that can be addressed by receiving a command from the memory controller, and (ii) output, via the command insertion terminal, the command or an indication of the condition such that the command is inserted into a command queue of the memory controller. The memory device can include a command terminal over which the memory device can receive the command from the memory controller after the command is inserted in the command queue. In some embodiments, the condition can be a memory region of the memory device requiring a refresh cycle, and the command can be a command to perform a refresh cycle on the memory region.
    Type: Application
    Filed: May 21, 2021
    Publication date: November 24, 2022
    Inventor: Sujeet Ayyapureddi
  • Publication number: 20220365889
    Abstract: Memory systems with a communications bus (and associated systems, devices, and methods) are disclosed herein. In one embodiment, a memory device includes an input/output terminal separate from data terminals of the memory device. The input/output terminal can be operably connected to a memory controller via a communications bus. The memory device can be configured to initiate a communication with the memory controller by outputting a signal via the input/output terminal and/or over the communications bus. The memory device can be configured to output the signal in accordance with a clock signal that is different from a second clock signal user to output or receive data signals via the data terminals. In some embodiments, the memory device is configured to initiate communications over the communication bus only when it possesses a communication token. The communication token can be transferred between memory devices operably connected to the communications bus.
    Type: Application
    Filed: May 12, 2021
    Publication date: November 17, 2022
    Inventor: Sujeet Ayyapureddi
  • Patent number: 11482275
    Abstract: Apparatuses, systems, and methods for dynamically allocated aggressor detection. A memory may include an aggressor address storage structure which tracks access patterns to row addresses and their associated bank addresses. These may be used to determine if a row and bank address received as part of an access operation are an aggressor row and bank address. The aggressor row address may be used to generate a refresh address for a bank identified by the aggressor bank address. Since the aggressor storage structure tracks both row and bank addresses, its storage space may be dynamically allocated between banks based on access patterns to those banks.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: October 25, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Sujeet Ayyapureddi, Donald M. Morgan
  • Publication number: 20220293166
    Abstract: Apparatuses, systems, and methods for sketch circuits for refresh binning. The rows of a memory may have different information retention times. The row addresses may be sorted into different bins based on these information retention times. In order to store information about which row addresses are associated with which bins a sketch circuit may be used. When an address is generated as part of a refresh operation, it may be used to generate a number of different hash values, which may be used to index entries in a storage structure. The entries may indicate which bin the address is associated with. Based on the binning information, the memory may refresh the address at different rates (e.g., by determining whether to provide the address as a refresh address or not).
    Type: Application
    Filed: March 15, 2021
    Publication date: September 15, 2022
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Sujeet Ayyapureddi, Donald M. Morgan
  • Publication number: 20220230672
    Abstract: Apparatuses, systems, and methods for dynamically allocated aggressor detection. A memory may include an aggressor address storage structure which tracks access patterns to row addresses and their associated bank addresses. These may be used to determine if a row and bank address received as part of an access operation are an aggressor row and bank address. The aggressor row address may be used to generate a refresh address for a bank identified by the aggressor bank address. Since the aggressor storage structure tracks both row and bank addresses, its storage space may be dynamically allocated between banks based on access patterns to those banks.
    Type: Application
    Filed: January 20, 2021
    Publication date: July 21, 2022
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Sujeet Ayyapureddi, Donald M. Morgan
  • Publication number: 20220223195
    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described in which waterfall attacks can be prevented from degrading data by alerting a memory controller that the memory device requests time to perform internal management operations, and should not be sent any further commands (e.g., activate commands) for a predetermined amount of time. In one embodiment, a memory device includes an external pin, a mode register, a memory array including a plurality of rows of memory cells, and circuitry configured to: determine that a criterion to perform an internal management operation on a subset of the plurality of rows has been met, transmit, in response to determining the criterion has been met, a signal to the external pin, determine a duration corresponding to the internal management operation, and write a bit value indicative of the determined duration to the mode register.
    Type: Application
    Filed: December 7, 2021
    Publication date: July 14, 2022
    Inventors: Sujeet Ayyapureddi, Randall J. Rooney
  • Publication number: 20220223596
    Abstract: Systems, methods and apparatus are provided for decoupling capacitors for an array of vertically stacked memory cells. Embodiments provide that the decoupling capacitors are electrically coupled to a power bus.
    Type: Application
    Filed: January 8, 2021
    Publication date: July 14, 2022
    Inventor: Sujeet Ayyapureddi
  • Patent number: 11386946
    Abstract: Apparatuses and methods for tracking all row accesses in a memory device over time may be used to identify rows which are being hammered so that ‘victim’ rows may be identified and refreshed. A register stack may include a number of count values, each of which may track a number of accesses to a portion of the word lines of the memory device. Anytime a row within a given portion is accessed, the associated count value may be incremented. When a count value exceeds a first threshold, a second stack with a second number of count values may be used to track numbers of accesses to sub-portions of the given portion. When a second count value exceeds a second threshold, victim addresses may be provided to refresh the victim word lines associated with any of the word lines within the sub-portion.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: July 12, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Sujeet Ayyapureddi, Donald M. Morgan
  • Patent number: 11342041
    Abstract: Apparatuses, systems, and methods for probabilistic data structures for error tracking. A memory device may include an error code correction (ECC) circuit which determines if data read from a memory array includes an error. If it does, the row address associated with the read data is provided to an error tracking circuit. The error tracking circuit may use probabilistic data structures, such as multiple count values, each indexed by different hash values of the row address. The count values may be used to determine if a given row address is repeatedly associated with errors. The memory may store these identified problem addresses in a data storage structure for example for diagnostic and/or repair purposes.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: May 24, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Sujeet Ayyapureddi
  • Patent number: 11309010
    Abstract: Apparatuses, systems, and methods for a memory-directed access pause. A controller may perform access operations on a memory by providing commands and addresses. The memory may monitor the addresses to determine if one or more forms of attack (deliberate or inadvertent) is occurring. If an attack is detected, the memory may issue an alert signal (e.g., along an alert bus) and also provide pause data (e.g., along a data bus). The pause data may specify a length of time, and responsive to the alert and the pause data, the controller may suspend access operations on the memory for the length of time specified in the pause data. The memory may use the time when access operations are paused to refresh itself, for example to heal the damage caused by the attack).
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: April 19, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Sujeet Ayyapureddi