Patents by Inventor Suk-Joo Lee

Suk-Joo Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090274980
    Abstract: A method of forming fine patterns of a semiconductor device according to a double patterning process that uses acid diffusion is provided. In this method, a plurality of first mask patterns are formed on a substrate so as to be separated from one another. A capping film including an acid source is formed on sidewalls and an upper surface of each of the plurality of first mask patterns. A second mask layer is formed on the capping films. A plurality of acid diffused regions are formed within the second mask layer by diffusing acid obtained from the acid source from the capping films into the second mask layer. A plurality of second mask patterns are formed of residual parts of the second mask layer which remain in the first spaces after removing the acid diffused regions of the second mask layer.
    Type: Application
    Filed: November 10, 2008
    Publication date: November 5, 2009
    Inventors: Yool Kang, Suk-joo Lee, Jung-hyeon Lee, Shi-yong Yi
  • Publication number: 20090087758
    Abstract: Design rules for circuit patterns of a semiconductor device are identified, and schematic layouts of the circuit patterns are generated according to the design rules. Lithography friendly layout (LFL) circuit patterns are generated from the schematic layouts. Target layout circuit patterns are generated from the LFL circuit patterns. Optical proximity effect correction (OPC) is performed on the target layout circuit patterns to generate OPC circuit patterns. A mask is fabricated from the OPC circuit patterns, and may be used fabricate a semiconductor device.
    Type: Application
    Filed: September 26, 2008
    Publication date: April 2, 2009
    Inventors: Sung-soo Suh, Suk-joo Lee, Yong-hee Park, Mi-kyeong Lee
  • Publication number: 20090013303
    Abstract: Provided are a method of creating a mask layout image from a target image, a computer readable storage medium having stored thereon a computer program for executing the method, and an imaging system. The method includes reading all or a part of a target image to be transcribed on a substrate; defining a mask data set including a plurality of pixels having a predetermined transmittance characteristic; defining a weighting function having a non-zero value within a critical range; defining a convolution kernel determined by an illumination meter; and creating the mask layout image that minimizes an image fitting function by using the weighting function and the convolution kernel.
    Type: Application
    Filed: July 3, 2008
    Publication date: January 8, 2009
    Inventors: Chan Hwang, Han-Ku Cho, Suk-joo Lee
  • Patent number: 7452825
    Abstract: In the method of forming a mask structure, a first mask is formed on a substrate where the first mask includes a first mask pattern having a plurality of mask pattern portions having openings therebetween and a second mask pattern having a corner portion of which an inner side wall that is curved. A sacrificial layer is formed on the first mask. A hard mask layer is formed on the sacrificial layer. After the hard mask layer is partially removed until the sacrificial layer adjacent to the corner portion is exposed, a second mask is formed from the hard mask layer remaining in the space after removing the sacrificial layer. A minute pattern having a fine structure may be easily formed on the substrate.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: November 18, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Doo-Youl Lee, Han-Ku Cho, Suk-Joo Lee, Gi-Sung Yeo, Cha-Won Koh, Sung-Gon Jung
  • Publication number: 20080230929
    Abstract: Provided are an overlay mark of a semiconductor device and a semiconductor device including the overlay mark. The overlay mark includes: reference marks formed in rectangular shapes comprising sides in which fine patterns are formed; and comparison marks formed as rectangular shapes which are smaller than the rectangular shapes of the reference marks and formed of fine patterns, wherein the number of comparison marks is equal to the number of reference marks, wherein the reference marks and the comparison marks are formed on different thin films formed on a semiconductor substrate to be used to inspect alignment states of the different thin films, and the overlay mark reflects an effect of aberration of patterns of memory cells through the fine patterns during a calculation of MR (mis-registration).
    Type: Application
    Filed: March 5, 2008
    Publication date: September 25, 2008
    Inventors: Jang-ho Shin, Chan-hoon Park, Jung-Hyeon Lee, Suk-joo Lee, Hyun-tae Kang, Jeong-hee Cho, Young-hoon Song
  • Publication number: 20080206686
    Abstract: A method of forming fine patterns on a semiconductor substrate includes forming a first pattern, including first line patterns having a feature size F and an arbitrary pitch P, and forming a second pattern, including second line patterns disposed between adjacent first line patterns, to form a fine pattern having a half pitch P/2, the first and second line patterns being repeated in the first direction. A gap is formed in at least one first line pattern in a second direction, perpendicular to the first direction, to connect second line patterns positioned on each side of the first line pattern through the gap. At least one jog pattern, extending in the first direction, is formed from at least one first line pattern adjacent to the connected second line patterns. The jog pattern causes a gap in at least one of the connected second line patterns in the second direction.
    Type: Application
    Filed: July 24, 2007
    Publication date: August 28, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Doo-youl LEE, Han-ku CHO, Suk-joo LEE, Gi-sung YEO, Pan-suk KWAK, Min-jong HONG
  • Patent number: 7403276
    Abstract: A photomask for measuring lens aberration, a method of manufacturing the photomask, and a method of measuring lens aberration using the photomask are provided. In an embodiment, the photomask includes a transparent substrate having first and second surfaces. A reference pattern group and an encoded pattern group are formed on the second surface of the transparent substrate, spaced apart from each other. An aperture that includes a Fresnel zone is formed to face the second surface on the second surface of the transparent substrate. Light throughput and measurement efficiency are improved.
    Type: Grant
    Filed: March 23, 2006
    Date of Patent: July 22, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jang-Ho Shin, Han-Ku Cho, Sang-Gyun Woo, Suk-Joo Lee
  • Publication number: 20080124931
    Abstract: A method for forming fine patterns of a semiconductor device includes forming an etching film on a substrate having first and second areas, forming first mask patterns on the substrate to have a first pattern density in the first area and a second pattern density in the second area, forming first capping patterns between the first mask patterns, forming second capping patterns between the first mask patterns, such that recess areas are formed between second capping patterns, and such that a first etching pattern is defined to include the first and second capping patterns, forming second mask patterns in the recess areas to include the first and second mask patterns, removing one of the first and second etching patterns, such that a single etching pattern is remaining on the substrate, and etching the etching film using the remaining etching pattern as an etch mask to form etching film patterns.
    Type: Application
    Filed: October 30, 2007
    Publication date: May 29, 2008
    Inventors: Doo-youl Lee, Pan-suk Kwak, Sung-gon Jung, Jung-hyeon Lee, Suk-joo Lee, Cha-won Koh, Ji-young Lee
  • Publication number: 20080106719
    Abstract: Provided are a compensating mask, a multi-optical system using the compensating mask, and a method of compensating for a 3-dimensional (3-D) mask effect using the compensating mask. Methods of compensating for a 3-D mask effect using a compensating mask may include generating a first kernel corresponding to a normal mask used for forming a minute pattern, generating a second kernel corresponding to a compensating mask, mixing the first kernel corresponding to the normal mask with the second kernel corresponding to the compensating mask, and generating a multi-optical system kernel corresponding to mixing the first kernel and the second kernel.
    Type: Application
    Filed: October 26, 2007
    Publication date: May 8, 2008
    Inventors: Sung-soo Suh, Suk-joo Lee, Han-ku Cho, Yong-jin Chun, Sung-woo Lee, Young-chang Kim
  • Publication number: 20080076047
    Abstract: A method of forming an image contour for predicting a pattern image formed on a wafer from a layout of a semiconductor device includes: forming a basic layout for a semiconductor device; performing an optical proximity effect correction (OPC) on the basic layout to form an OPC layout; defining nonlinear regions and linear regions of the basic layout; emulating the nonlinear regions of the basic layout using the OPC layout to form an image contour of the nonlinear regions; determining the linear regions of the basic layout as an image contour of the linear regions; and combining the image contour of the nonlinear regions and image contour of the linear regions to form an image contour of the entire semiconductor device.
    Type: Application
    Filed: October 27, 2006
    Publication date: March 27, 2008
    Inventors: Yong-jin Chun, Doo-youl Lee, Moon-hyun Yoo, Suk-joo Lee
  • Publication number: 20080067550
    Abstract: Provided are a flash memory device and a method of manufacturing the same. The flash memory device includes strings. Each of the strings has a string selection line, a ground selection line, and an odd number of word lines formed between the string selection line and the ground selection line.
    Type: Application
    Filed: October 31, 2006
    Publication date: March 20, 2008
    Inventors: Doo-youl Lee, Han-ku Cho, Suk-joo Lee, Gi-sung Yeo, Cha-won Koh, Pan-suk Kwak
  • Publication number: 20080057610
    Abstract: In the method of forming a mask structure, a first mask is formed on a substrate where the first mask includes a first mask pattern having a plurality of mask pattern portions having openings therebetween and a second mask pattern having a corner portion of which an inner side wall that is curved. A sacrificial layer is formed on the first mask. A hard mask layer is formed on the sacrificial layer. After the hard mask layer is partially removed until the sacrificial layer adjacent to the corner portion is exposed, a second mask is formed from the hard mask layer remaining in the space after removing the sacrificial layer. A minute pattern having a fine structure may be easily formed on the substrate.
    Type: Application
    Filed: October 30, 2006
    Publication date: March 6, 2008
    Inventors: Doo-Youl Lee, Han-Ku Cho, Suk-Joo Lee, Gi-Sung Yeo, Cha-Won Koh, Sung-Gon Jung
  • Publication number: 20070287299
    Abstract: A method of forming a semiconductor device includes forming a first mask pattern on a target layer, the first mask pattern exposing a first portion of the target layer, forming an intermediate material layer, including depositing an intermediate material layer film on a side of the first mask pattern and the first portion of the target layer, and thinning the intermediate material layer film to form the intermediate material layer, forming a second mask pattern that exposes a second portion of the intermediate material layer, removing the exposed second portion of the intermediate material layer to expose the target layer, and patterning the target layer using the first and second mask patterns as patterning masks.
    Type: Application
    Filed: February 28, 2007
    Publication date: December 13, 2007
    Inventors: Doo-youl Lee, Suk-joo Lee, Yool Kang, Han-ku Cho, Chang-jin Kang, Jae-ok Yoo, Sung-chan Park
  • Publication number: 20070264584
    Abstract: A pattern arrangement method of a semiconductor device is provided. In the pattern arrangement method, patterns are classified according to effective pitches and critical dimensions, and pattern dispersion is predicted according to the effective pitches and the critical dimensions by using a statistical analysis of process parameters. Two-dimensional coordinates of the effective pitches and the critical dimensions are constructed, and a dispersion map is made by arranging the predicted pattern dispersion on the corresponding coordinates. By arranging design patterns within a tolerance region of the dispersion map, the patterns satisfying the dispersion tolerance according to the significance of the layer and the design requirements can be arranged.
    Type: Application
    Filed: February 13, 2007
    Publication date: November 15, 2007
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: In-Sung KIM, Sung-Soo SUH, Suk-Joo LEE, Sung-Hwan BYUN, Sang-Wook KIM
  • Publication number: 20070178393
    Abstract: A reflective photomask for EUV light is disclosed. The reflective photomask may include a projecting pattern selectively formed on a substrate and a reflective layer on the substrate and the projecting pattern.
    Type: Application
    Filed: January 23, 2007
    Publication date: August 2, 2007
    Inventors: Jin-Hong Park, Han-Ku Cho, Seong-Sue Kim, Sang-Gyun Woo, Suk-Joo Lee
  • Publication number: 20060216616
    Abstract: A photomask for measuring lens aberration, a method of manufacturing the photomask, and a method of measuring lens aberration using the photomask are provided. In an embodiment, the photomask includes a transparent substrate having first and second surfaces. A reference pattern group and an encoded pattern group are formed on the second surface of the transparent substrate, spaced apart from each other. An aperture that includes a Fresnel zone is formed to face the second surface on the second surface of the transparent substrate. Light throughput and measurement efficiency are improved.
    Type: Application
    Filed: March 23, 2006
    Publication date: September 28, 2006
    Inventors: Jang-Ho Shin, Han-Ku Chu, Sang-Gyun Woo, Suk-Joo Lee
  • Publication number: 20060154155
    Abstract: An optical mask for use with an exposure beam includes a mask substrate adapted to be placed on a traveling path of the exposure beam. A reference pattern is formed on the mask substrate. The reference pattern is adapted to direct the exposure beam to travel in a predetermined reference direction. A comparative pattern is formed on the mask substrate. The comparative pattern is adapted to direct the exposure beam to travel in a direction inclined at a predetermined angle with respect to the reference direction.
    Type: Application
    Filed: December 19, 2005
    Publication date: July 13, 2006
    Inventors: Chan Hwang, Suk-Joo Lee, Han-Ku Cho, Sang-Gyun Woo
  • Publication number: 20060147835
    Abstract: A chemically-amplified photoresist composition includes a polymer resin, a photo acid generator (PAG), and a thermal acid generator (TAG), where a thermal deprotection temperature of the polymer resin is greater than an acid generation temperature of the TAG. The photoresist composition may be utilized in a photolithography process which includes subjecting a layer of the photoresist composition to photon exposure which causes the PAG to decompose into acid, subjecting the photon-exposed layer of the photo resist composition to a heat treatment which causes the TAG to decompose into acid, and subjecting the heat-treated layer of photoreist composition to a post-exposure bake (PEB) at a temperature which is greater than the temperature of the heat treatment.
    Type: Application
    Filed: December 5, 2005
    Publication date: July 6, 2006
    Inventors: Sook Lee, Min-jeong Oh, Suk-joo Lee
  • Publication number: 20060127816
    Abstract: The present invention provides a double photolithography method in which, after a first photoresist pattern including a crosslinkable agent is formed on a semiconductor substrate, a crosslinkage is formed in a molecular structure of the first photoresist pattern. A second photoresist film may be formed on a surface of the semiconductor substrate on which the crosslinked first photoresist patterns are formed. Second photoresist patterns may be formed by exposing, post-exposure baking, and developing the second photoresist film.
    Type: Application
    Filed: December 7, 2005
    Publication date: June 15, 2006
    Inventors: Yool Kang, Han-ku Cho, Sang-Gyun Woo, Suk-Joo Lee, Man-Hyung Ryoo, Mitsuhiro Hata, Hyung-Rae Lee
  • Publication number: 20060115746
    Abstract: A focus monitoring mask includes a transparent substrate, e.g., a quartz layer. A light blocking film, e.g., a chromium-containing film, is disposed on the transparent substrate and has an opening therein. A transparent unit is disposed in a portion of the substrate exposed by the opening. The transparent unit includes a first phase shifter, a second phase shifter and a third phase shifter arranged adjacently in order of amount of phase shift. The second phase shifter is configured to provide an about 180° phase difference with respect to the first phase shifter. The third phase shifter is configured to provide a phase difference other than about 0° and about 180° with respect to the first phase shifter. The transparent unit may further include a fourth phase shifter having a fourth phase difference with respect to the first phase shifter that differs from about 0°, about 180° and the phase difference provided by the third phase shifter.
    Type: Application
    Filed: November 16, 2005
    Publication date: June 1, 2006
    Inventors: Sung-Won Choi, Suk-joo Lee, Ho-chul Kim, Han-ku Cho, Sang-gyun Woo