Patents by Inventor Suk-Joo Lee

Suk-Joo Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060079067
    Abstract: A method of fabricating a semiconductor device includes forming a material layer on a substrate, forming a mask layer on the material layer, and implanting ions into the mask layer to reduce light absorption thereof. An alignment key may be formed between the material layer and the substrate, and a location of the alignment key may be optically determined through the implanted mask layer. The implanted mask layer is patterned to define a mask pattern, and the material layer is patterned using the mask pattern as an etching mask. Related devices are also discussed.
    Type: Application
    Filed: September 26, 2005
    Publication date: April 13, 2006
    Inventors: Jang-Ho Shin, Suk-Joo Lee, Han-Ku Cho, Sang-Gyun Woo
  • Patent number: 6673706
    Abstract: A photoresist pattern is formed, without being exposed, by using photoresist having a residual layer proportion characteristic by which the photoresist dissolves at a suitable rate in a developing solution. First, a target layer to be patterned and a photoresist layer are sequentially formed on a substrate having a pattern that defines a step on the substrate. Some of the photoresist layer is treated with the developing solution, to thereby form a photoresist pattern whose upper surface is situated beneath the step and hence, exposes part of the target layer. Next, the exposed part of the target layer, and the photoresist pattern are removed. A silicidation process may be carried out thereafter on the area(s) from which the target layer has been removed. The method is relatively simple because it does not involve an exposure process. Furthermore, the method can be used to manufacture devices having very fine linewidths, i.e.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: January 6, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-yong Yoo, Dae-youp Lee, Jeung-woo Lee, Suk-joo Lee, Jae-han Lee
  • Patent number: 6571384
    Abstract: A method of forming fine patterns in a semiconductor device through a double photo lithography process. A layer to be etched and a hard mask layer are sequentially formed on a semiconductor substrate. A first photo resist pattern is formed on the hard mask layer. A first hard mask layer pattern is formed by etching the hard mask layer using the first photo resist pattern. After the first photo resist pattern is removed, a second photo resist pattern is formed on the resultant structure. A second hard mask layer pattern is formed by etching the first hard mask layer pattern using the second photo resist pattern. The layer to be etched is then etched using the second hard mask layer pattern after the second photo resist pattern has been removed, resulting in patterns have line edges without rounding.
    Type: Grant
    Filed: May 3, 2001
    Date of Patent: May 27, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hye-Soo Shin, Suk-Joo Lee, Jeung-Woo Lee, Dae-Youp Lee
  • Publication number: 20020119403
    Abstract: A photoresist pattern is formed, without being exposed, by using photoresist having a residual layer proportion characteristic by which the photoresist dissolves at a suitable rate in a developing solution. First, a target layer to be patterned and a photoresist layer are sequentially formed on a substrate having a pattern that defines a step on the substrate. Some of the photoresist layer is treated with the developing solution, to thereby form a photoresist pattern whose upper surface is situated beneath the step and hence, exposes part of the target layer. Next, the exposed part of the target layer, and the photoresist pattern are removed. A silicidation process may be carried out thereafter on the area(s) from which the target layer has been removed. The method is relatively simple because it does not involve an exposure process. Furthermore, the method can be used to manufacture devices having very fine linewidths, i.e.
    Type: Application
    Filed: December 21, 2001
    Publication date: August 29, 2002
    Inventors: Ji-Yong Yoo, Dae-Youp Lee, Jeung-Woo Lee, Suk-Joo Lee, Jae-Han Lee
  • Publication number: 20020059557
    Abstract: A method of forming fine patterns in a semiconductor device through a double photo lithography process. A layer to be etched and a hard mask layer are sequentially formed on a semiconductor substrate. A first photo resist pattern is formed on the hard mask layer. A first hard mask layer pattern is formed by etching the hard mask layer using the first photo resist pattern. After the first photo resist pattern is removed, a second photo resist pattern is formed on the resultant structure. A second hard mask layer pattern is formed by etching the first hard mask layer pattern using the second photo resist pattern. The layer to be etched is then etched using the second hard mask layer pattern after the second photo resist pattern has been removed, resulting in patterns have line edges without rounding.
    Type: Application
    Filed: May 3, 2001
    Publication date: May 16, 2002
    Inventors: Hye-Soo Shin, Suk-Joo Lee, Jeung-Woo Lee, Dae-Youp Lee
  • Publication number: 20020047209
    Abstract: A method of forming a contact hole for a dual damascene interconnection of a semiconductor device includes forming a first photoresist layer pattern on an insulating layer of a semiconductor substrate, the first photoresist layer pattern having a first opening with a first width. A groove having the first width to a prescribed depth of the insulating layer is formed by performing an etching process using the first photoresist layer pattern as an etch mask. A second photoresist layer pattern on the insulating layer having the groove therein is formed. The second photoresist layer has a second opening with a second width, wherein the second width is substantially equal to or larger than the first width of the groove. A contact hole exposing the semiconductor substrate is formed by performing an etching process using the second photoresist layer pattern as an etch mask.
    Type: Application
    Filed: October 4, 2001
    Publication date: April 25, 2002
    Inventors: Suk Joo Lee, Hee Hong Yang, Jeong Lim Nam