Patents by Inventor Sumana Pal

Sumana Pal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8824215
    Abstract: A data storage circuit for receiving and holding a data value includes an input stage configured to receive a data value in response to the precharge phase changing to an evaluation phase and to hold the data value during the evaluation phase. An output stage has an output latching element for holding the value, two switching devices for updating the output latching element and an output. The switching devices each being controlled by respective signals from dual data lines, wherein, in response to the data value held in the input stage being a logical one, the first switching device updates the output latching element with a value indicative of the logical one and in response to the data value held in the input stage being a logical zero, the second switching device updates the output latching element with a value indicative of the logical zero.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: September 2, 2014
    Assignee: ARM Limited
    Inventors: Marlin Wayne Frederick, Jr., Akhtar Waseem Alam, Sumana Pal
  • Patent number: 8427214
    Abstract: A master-slave flip-flop circuit is provided with a retention capability to support operation in both a normal mode and a retention mode. During the retention mode the retention circuitry drives the output signal via either a first path 16 or a second path 22, 24, 4, 10 in dependence upon the phase of the clock signal. During both phases of the clock signal the output signal is driven in a well defined state to reflect the signal stored within the retention circuitry. There is thus provided a clock independent retention master-slave flip-flop circuit. Both high density and high speed variants of the flip-flop circuit may use the technique.
    Type: Grant
    Filed: December 28, 2010
    Date of Patent: April 23, 2013
    Assignee: ARM Limited
    Inventor: Sumana Pal
  • Patent number: 8421513
    Abstract: A master-slave flip-flop circuit comprises a master stage for retaining a master signal, a slave stage for retaining a slave signal and a retention stage. During a normal mode of operation, the retention stage captures a retention signal having a value dependent upon the slave signal. During a retention mode of operation, the retention stage isolates the retention signal from changes in the stage signal and retains the retention signal. During the retention mode the retention stage also provides a master restore signal to the master stage and provides a slave restore signal to the slave stage. The master restore signal and the slave restore signal have values dependent on the retention signal for configuring the master stage and slave stage such that the master and slave signals have values corresponding to the retention signal.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: April 16, 2013
    Assignee: ARM Limited
    Inventor: Sumana Pal
  • Publication number: 20130064019
    Abstract: A data storage circuit for receiving and holding a data value includes an input stage configured to receive a data value in response to the precharge phase changing to an evaluation phase and to hold the data value during the evaluation phase. An output stage has an output latching element for holding the value, two switching devices for updating the output latching element and an output. The switching devices each being controlled by respective signals from dual data lines, wherein, in response to the data value held in the input stage being a logical one, the first switching device updates the output latching element with a value indicative of the logical one and in response to the data value held in the input stage being a logical zero, the second switching device updates the output latching element with a value indicative of the logical zero.
    Type: Application
    Filed: February 1, 2012
    Publication date: March 14, 2013
    Applicant: ARM LIMITED
    Inventors: Marlin Wayne FREDERICK, JR., Akhtar Waseem Alam, Sumana Pal
  • Publication number: 20110298517
    Abstract: A master-slave flip-flop circuit comprises a master stage for retaining a master signal, a slave stage for retaining a slave signal and a retention stage. During a normal mode of operation, the retention stage captures a retention signal having a value dependent upon the slave signal. During a retention mode of operation, the retention stage isolates the retention signal from changes in the stage signal and retains the retention signal. During the retention mode the retention stage also provides a master restore signal to the master stage and provides a slave restore signal to the slave stage. The master restore signal and the slave restore signal have values dependent on the retention signal for configuring the master stage and slave stage such that the master and slave signals have values corresponding to the retention signal.
    Type: Application
    Filed: June 1, 2011
    Publication date: December 8, 2011
    Applicant: ARM LIMITED
    Inventor: Sumana Pal
  • Publication number: 20110298516
    Abstract: A master-slave flip-flop circuit is provided with a retention capability to support operation in both a normal mode and a retention mode. During the retention mode the retention circuitry drives the output signal via either a first path 16 or a second path 22, 24, 4, 10 in dependence upon the phase of the clock signal. During both phases of the clock signal the output signal is driven in a well defined state to reflect the signal stored within the retention circuitry. There is thus provided a clock independent retention master-slave flip-flop circuit. Both high density and high speed variants of the flip-flop circuit may use the technique.
    Type: Application
    Filed: December 28, 2010
    Publication date: December 8, 2011
    Applicant: ARM LIMITED
    Inventor: Sumana Pal