Patents by Inventor Sumihiro Miura

Sumihiro Miura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9690664
    Abstract: The present invention provides a storage system capable of preventing data loss when power failure or other failures occur to an external power supply, by determining whether the capacity corresponding to the write data can be saved from a volatile memory to a nonvolatile memory based on a charged capacity of a battery used as an internal power supply and a non-backed-up (not yet backed-up) data capacity from the volatile memory to the nonvolatile memory, when storing data from a host computer or a system drive to the volatile memory of the storage system. If it is determined that saving of data is possible, an area corresponding to the write data capacity is allocated in the volatile memory and data is written to the allocated area, but if it is determined that saving of data is not possible, the writing of data is suppressed.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: June 27, 2017
    Assignee: HITACHI, LTD.
    Inventors: Kyohei Ide, Naoki Moritoki, Sumihiro Miura
  • Publication number: 20160259726
    Abstract: The present invention provides a storage system capable of preventing data loss when power failure or other failures occur to an external power supply, by determining whether the capacity corresponding to the write data can be saved from a volatile memory to a nonvolatile memory based on a charged capacity of a battery used as an internal power supply and a non-backed-up (not yet backed-up) data capacity from the volatile memory to the nonvolatile memory, when storing data from a host computer or a system drive to the volatile memory of the storage system. If it is determined that saving of data is possible, an area corresponding to the write data capacity is allocated in the volatile memory and data is written to the allocated area, but if it is determined that saving of data is not possible, the writing of data is suppressed.
    Type: Application
    Filed: March 13, 2014
    Publication date: September 8, 2016
    Applicant: HITACHI, LTD.
    Inventors: Kyohei IDE, Naoki MORITOKI, Sumihiro MIURA
  • Patent number: 8572336
    Abstract: A storage control apparatus of the present invention is able to duplicatively manage data in a cache memory even during maintenance work. When a memory package CMPK3 specified by a user is removed from the apparatus 1 (S2), a microprocessor 2 changes a pair that has been configured using CMPK2 and CMPK3 to a pair of CMPK2 and a free area of a CMPK1. As a result, received data (S5) is respectively written to multiple cache memories (S6, S7), and duplicatively managed.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: October 29, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Masanori Fujii, Sumihiro Miura
  • Publication number: 20130097379
    Abstract: It is provided a storage system for storing data requested by a host computer to be written, the storage system comprising: at least one processor, a cache memory and a cache controller. The cache memory includes a first memory which can be accessed by way of either access that can specify an access range by a line or access that continuously performs a read and a write. The cache controller includes a second memory which has a higher flexibility than the first memory in specifying an access range. The cache controller determines an address of an access destination upon reception of a request for an access to the cache memory from the at least one processor, and switches a request for an access to a specific address into an access to a corresponding address in the second memory.
    Type: Application
    Filed: October 13, 2011
    Publication date: April 18, 2013
    Applicant: HITACHI, LTD.
    Inventors: Kyohei Ide, Sumihiro Miura, Naoki Moritoki
  • Patent number: 8412884
    Abstract: It is provided a storage system for storing data requested by a host computer to be written, the storage system comprising: at least one processor, a cache memory and a cache controller. The cache memory includes a first memory which can be accessed by way of either access that can specify an access range by a line or access that continuously performs a read and a write. The cache controller includes a second memory which has a higher flexibility than the first memory in specifying an access range. The cache controller determines an address of an access destination upon reception of a request for an access to the cache memory from the at least one processor, and switches a request for an access to a specific address into an access to a corresponding address in the second memory.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: April 2, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Kyohei Ide, Sumihiro Miura, Naoki Moritoki
  • Patent number: 8255624
    Abstract: A storage apparatus and its control method capable of shortening data save time at the time of power shutdown are suggested. The storage apparatus includes a processor for controlling reading/writing user data from/to a disk device(s), and a cache memory for storing user data sent and received between a channel adapter and a the disk adapter and control data used by the processor, wherein the control data is sorted into and stored in the nonvolatile memory or the volatile memory according to its update frequency.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: August 28, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Masanori Fujii, Tsukasa Nishimura, Sumihiro Miura, Hiraki Mikami
  • Publication number: 20120096229
    Abstract: A storage control apparatus of the present invention is able to duplicatively manage data in a cache memory even during maintenance work. When a memory package CMPK3 specified by a user is removed from the apparatus 1 (S2), a microprocessor 2 changes a pair that has been configured using CMPK2 and CMPK3 to a pair of CMPK2 and a free area of a CMPK1. As a result, received data (S5) is respectively written to multiple cache memories (S6, S7), and duplicatively managed.
    Type: Application
    Filed: October 14, 2010
    Publication date: April 19, 2012
    Applicant: HITACHI, LTD.
    Inventors: Masanori Fujii, Sumihiro Miura
  • Patent number: 8117391
    Abstract: A storage system, which is coupled to a computer, includes a storage device, a controller, a plurality of cache memory units, and a connecting unit. Each of the plurality of cache memory units includes: a cache memory for storing data; an auxiliary storage device for holding a content of data even after shutdown of power; and a cache controller for controlling an input/output of data to/from the cache memory and the auxiliary storage device. The cache controller store data stored in the cache memory, which is divided into a plurality of parts, into a plurality of the auxiliary storage devices included in the plurality of cache memory units.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: February 14, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Masanori Fujii, Tsukasa Nishimura, Sumihiro Miura, Yoshinori Okubo
  • Publication number: 20110271048
    Abstract: A storage apparatus and its control method capable of shortening data save time at the time of power shutdown are suggested. The storage apparatus includes a processor for controlling reading/writing user data from/to a disk device(s), and a cache memory for storing user data sent and received between a channel adapter and a the disk adapter and control data used by the processor, wherein the control data is sorted into and stored in the nonvolatile memory or the volatile memory according to its update frequency.
    Type: Application
    Filed: December 17, 2009
    Publication date: November 3, 2011
    Applicant: HITACHI, LTD.
    Inventors: Masanori Fuji, Tsukasa Nishimura, Sumihiro Miura, Hiraki Mikami
  • Patent number: 8024516
    Abstract: A storage apparatus sets up part of non-volatile cache memory as a cache-resident area, and in an emergency such as an unexpected power shutdown, backs up dirty data of data cached in volatile memory to an area other than the cache-resident area in the non-volatile cache memory, together with the relevant cache management information. Further, the storage apparatus monitors the amount of the dirty data in the volatile cache memory so that the dirty data cached in the volatile cache memory is reliably contained in a backup area in the non-volatile memory, and when the dirty data amount exceeds a predetermined threshold value, the storage apparatus releases the cache-resident area to serve as the backup area.
    Type: Grant
    Filed: January 30, 2008
    Date of Patent: September 20, 2011
    Assignee: Hitachi, Ltd.
    Inventor: Sumihiro Miura
  • Publication number: 20100293331
    Abstract: A storage system, which is coupled to a computer, includes a storage device, a controller, a plurality of cache memory units, and a connecting unit. Each of the plurality of cache memory units includes: a cache memory for storing data; an auxiliary storage device for holding a content of data even after shutdown of power; and a cache controller for controlling an input/output of data to/from the cache memory and the auxiliary storage device. The cache controller store data stored in the cache memory, which is divided into a plurality of parts, into a plurality of the auxiliary storage devices included in the plurality of cache memory units.
    Type: Application
    Filed: October 8, 2008
    Publication date: November 18, 2010
    Inventors: Masanori Fujii, Tsukasa Nishimura, Sumihiro Miura, Yoshinori Okubo
  • Publication number: 20090077312
    Abstract: A storage apparatus sets up part of non-volatile cache memory as a cache-resident area, and in an emergency such as an unexpected power shutdown, backs up dirty data of data cached in volatile memory to an area other than the cache-resident area in the non-volatile cache memory, together with the relevant cache management information. Further, the storage apparatus monitors the amount of the dirty data in the volatile cache memory so that the dirty data cached in the volatile cache memory is reliably contained in a backup area in the non-volatile memory, and when the dirty data amount exceeds a predetermined threshold value, the storage apparatus releases the cache-resident area to serve as the backup area.
    Type: Application
    Filed: January 30, 2008
    Publication date: March 19, 2009
    Inventor: Sumihiro Miura
  • Patent number: 7383472
    Abstract: A disk array subsystem makes a diagnosis of a memory device while maintaining performance of a normal access to the memory device contained in a controller, thus enhancing reliability of the memory data. In the disk array subsystem having a disk drive and a controller, the controller has a cache unit and the cache unit has a memory device and a memory control unit. The memory control unit monitors status of memory access by means of a memory access state monitoring unit, issues a diagnosis request while normal access is not made to the memory device, makes access to the memory device for diagnosis of the memory data, and checks the data read from the memory device by using ECC and detects a data error.
    Type: Grant
    Filed: January 4, 2005
    Date of Patent: June 3, 2008
    Assignee: Hitachi, Ltd.
    Inventor: Sumihiro Miura
  • Patent number: 7055001
    Abstract: To receive a data input/output request from an information processor and writing data in a hard disk drive in accordance with the data input/output request, a storage array controller is provided with a circuit board having a nonvolatile memory functioning as a cache memory for storing the data to be read from or written in the hard disk drive and a circuit board mounting assembly to which the circuit board is removably mounted and in which the circuit board is provided with a removal information output circuit for outputting the circuit board removal information indicating that the circuit board is removed from the circuit board mounting assembly and a data erase circuit for erasing the data stored in the nonvolatile memory when the circuit board removal information is output from the removal information output circuit.
    Type: Grant
    Filed: March 26, 2004
    Date of Patent: May 30, 2006
    Assignee: Hitachi, Ltd.
    Inventor: Sumihiro Miura
  • Publication number: 20060101304
    Abstract: A disk array subsystem makes a diagnosis of a memory device while maintaining performance of a normal access to the memory device contained in a controller, thus enhancing reliability of the memory data. In the disk array subsystem having a disk drive and a controller, the controller has a cache unit and the cache unit has a memory device and a memory control unit. The memory control unit monitors status of memory access by means of a memory access state monitoring unit, issues a diagnosis request while normal access is not made to the memory device, makes access to the memory device for diagnosis of the memory data, and checks the data read from the memory device by using ECC and detects a data error.
    Type: Application
    Filed: January 4, 2005
    Publication date: May 11, 2006
    Inventor: Sumihiro Miura
  • Publication number: 20050177680
    Abstract: To provide a storage controller for receiving a data input/output request from an information processor and writing data in a hard disk drive in accordance with the data input/output request, which is provided with a circuit board having a nonvolatile memory functioning as a cache memory for storing the data to be read from or written in the hard disk drive and a circuit board setting portion to which the circuit board is removably set and in which the circuit board is provided with a removal information output circuit for outputting the circuit board removal information showing that the circuit board is removed from the circuit board setting portion and a data erase circuit for erasing the data stored in the nonvolatile memory when the circuit board removal information is output from the removal information output circuit.
    Type: Application
    Filed: March 26, 2004
    Publication date: August 11, 2005
    Inventor: Sumihiro Miura