Abstract: The first input terminal of a differential amplification type sense amplifier is connected to a first memory cell array and the second input terminal thereof is connected to a second memory cell array. Each of the first and second memory cell arrays is formed of a plurality of memory cells arranged in a matrix form. Each of the memory cells in the first memory cell array and a corresponding one of the memory cells in the second memory cell array are provided in the form of pair for each bit. Complementary data is programmed into the paired memory cells according to programming data. In the data readout operation, the potential of data read out from the paired memory cells is amplified by means of the differential amplification type sense amplifier. First and second loads are connected to the first and second input terminals of the differential amplification type sense amplifier.

Abstract: This invention provides a non-volatile semiconductor memory having a first node and a second node, the second node having a ground potential. The invention includes a plurality of non-volatile memory cells each having a drain and a threshold potential, the cells, for storing data written into the cells at a predetermined normal writing voltage. A plurality of bit lines, each memory cell being connected to one of the bit lines, transfer data to and from the memory cells. A circuit connected to the bit lines simultaneously tests the memory cells of all the bit lines at the normal writing voltage to detect changes in the threshold potential.

Abstract: A nonvolatile semiconductor memory according to this invention is so constructed that different data readout references are used in an ordinary readout mode and in a program verification mode. The different read-out references can be set by changing reference input potential VREF supplied to a differential sense amplifier for amplifying a potential derived onto a bit line from a memory cell, or by changing an input threshold level of a circuit for sensing the potential on the bit line. In this case, the readout reference in the program verification mode is set severe, or high, in comparison with that in the ordinary readout mode.

Abstract: A nonvolatile semiconductor memory of this invention is constituted to latch input data into data latch circuits and at the same time control the programming operation of the bit line load transistors when the chip enable signal is made active and a page programming power source voltage is set at the programming voltage, while the output enable signal is kept inactive. Further, when the output enable signal is made active or the programming power source voltage is set at a voltage different from the programming voltage, the data latch circuits are reset. The data latch circuits can be selectively specified by a preset combination of bits.

Abstract: A voltage level converting circuit for outputting an output signal of a write voltage level responsive to a read voltage level input signal comprises an inverter circuit biased with a power supply of the first voltage level. The input signal is supplied through a transfer gate circuit. A MOS transistor is provided between the input of the inverter circuit and a power supply of the write voltage level to pull-up the voltage level of the input to the inverter circuit responsive to the output of the inverter circuit. Another MOS transistor is provided between the output of the inverter circuit and ground to pull-down the output voltage level responsive to the input signal.

Abstract: A semiconductor memory device of the invention has a plurality of floating gate memory cells. A detector detects the data stored in a floating gate memory cell selected by a decoder and produces a corresponding detection signal. A load circuit amplifies the detection signal. The amplified detection signal is supplied to a differential amplifier. The differential amplifier compares the voltage of the amplified detection signal with a reference voltage from a reference voltage generator and produces a binary signal corresponding to the storage contents in the floating gate memory. The load circuit is a p-channel enhancement-type MOS transistor. The load transistor has a gate and drain which are connected to the node between the detector and the differential amplifier, and also has a source and substrate which receive a predetermined voltage.

Abstract: A second impurity diffusion layer is formed in a semiconductor substrate at a fixed distance from a first diffusion layer in the substrate. The diffusion layer is supplied with a program potential. An electrode is placed on the channel region between the first and second diffusion layers. Non-selected memory cells are prevented from becoming half-selected by electrically separating the first diffusion layer from the program potential according to signals from the electrode, resulting in substantial improvements in the reliability of the semiconductor device.

Abstract: A nonvolatile semiconductor memory of this invention is obtained by dividing a memory cell array in which EPROM cells are provided in a matrix form and a write circuit into a plurality of blocks, commonly connecting sources of cell transistors in each block of the memory cell array, and connecting the common source of each block to a ground node through a corresponding resistive component.

Abstract: A nonvolatile semiconductor memory device includes a power voltage select circuit that is comprised of first and second power source nodes, an output node, first and second depletion type MOS transistors connected in series between the first power source node and the output node, a third MOS transistor connected between an interconnection point between the first and second depletion type MOS transistors and the second power source node, and a fourth MOS transistor connected between the second power source node and the output node.

Abstract: A differential amplifier having input terminals connected to first and second nodes lying between the main nonvolatile memory cell section and the nonvolatile dummy cell circuit is used as a sense amplifier. The first and second nodes are pre-charged to a high potential level prior to the data readout operation. The memory cell section and the dummy cell circuit are set in the capacitively balanced condition, thereby making it possible to correctly read out data at a high speed.

Abstract: A nonvolatile semiconductor memory device comprising a matrix array of memory cells, word lines for driving the rows of memory cells, bit lines for reading data from columns of memory cells, a plurality of first MOS transistors provided for these bit lines, respectively, a second MOS transistor having a source coupled to the bit lines by the first MOS transistors, a drain coupled to a VCC terminal, and a gate connected to receive a predetermined bias voltage, a row decoder for selecting one of the word lines in accordance with a row-address signal, and a column decoder for turning on one of the first MOS transistors in accordance with a column-address signal.

Abstract: A semiconductor memory device includes a main memory cell array, a redundancy memory cell array, bonding pads for receiving an address signal, a row decoder for selecting a row of the main memory cell array in accordance with the row address signal, and an exchange controller connected to receive the address signal, which is programmable to inhibit the selective operation of the row decoder to select the row of the redundancy memory cell array, in response to specific address signals. The semiconductor memory device further includes bonding pads, each for receiving a test signal. The exchange controller is connected to receive the test signal for inhibiting the selective operation of the row decoder and selecting the row of the redundancy memory cell array, in response to the test signal.

Abstract: A nonvolatile semiconductor memory device is disclosed comprising a bit line connected to the drain of a memory cell transistor forming a nonvolatile memory cell, a first p-channel MOS transistor, the drain and gate of the first transistor being connected to a node, and the source of the first transistor being connected to a power source potential, second and third n-channel MOS transistors connected in series between the node and a reference potential, the drain and gate of the second transistor being interconnected, and the drain and gate of the third transistor being interconnected, and a fourth n-channel MOS transistor for controlling charging of the bit line, one terminal of the drain-source path of the fourth transistor being connected to the power source potential and the other terminal being connected to the bit line, and the gate of the fourth transistor being connected to the node.

Abstract: Disclosed is a nonvolatile semiconductor memory having a high access speed and high reliability. The memory includes a source diffusion region extending in one direction, a pair of first word lines arranged in parallel with the source diffusion region, such that the source diffusion region is interposed therebetween, drain diffusion regions disposed to face the source diffusion region, with the first word lines interposed therebetween, bit lines electrically connected to the drain diffusion regions and arranged to cross the first word lines, a channel region formed below each of the first word lines and positioned between the source diffusion region and the drain diffusion region, a floating gate electrode formed in an electrically floating manner above the channel region and below one of the pair of the first word lines, and a second word line formed above the source region and positioned between and electrically connected to the pair of first word lines.

Abstract: Each memory cell in an EPROM includes two memory cell transistors which share a common floating gate and have two separated drains, one of which is connected to a read bit line and the other of which is connected to write bit line. In this EPROM, the read memory cell transistor of the read bit line has a lower hot electron injection rate than the hot electron injection rate of the write memory cell transistor of the write bit line. A bit line voltage booster is connected to the read bit line.

Abstract: There is disclosed a semiconductor memory device comprising a memory cell connected to a bit line, and a clamp circuit comprising a load MOS transistor connected between a power source voltage and the bit line, for clamping the power source voltage and applying the clamped voltage to the bit line. The semiconductor memory device further comprises a bypass circuit connected between the bit line and a reference voltage, for bypassing from the bit line to the reference voltage an electric current the amount of which is substantially equal to that of a weak inversion current of the load MOS transistor flowing into said bit line.

Abstract: A semiconductor memory device in which the differential amplifier circuit compares a potential of a bit line to which memory cells storing information are connected with a reference potential of a dummy line to which a dummy cell is connected, and detects information stored in each of the memory cells. The semiconductor memory device comprises a circuit which discharges both the bit line and the dummy line to a low potential when the chip enable inverted signal is supplied. When the chip enable signal is supplied, therefore, the differential amplifier circuit can detect a difference between the bit line potential and the dummy line potential before the bit line is fully charged up. This makes it possible to produce the chip enable access time and to realize higher speed operations.

Abstract: In one aspect of the present invention, there is provided a video tape recorder system capable of finding a desired frame by carrying out a retrieval operation in two steps, coarse and fine, in which video tape on which is recorded addresses indicating respective locations on the tape is advanced at high speed using the upper digits of the addresses for coarse retrieval and then the tape is advanced at a speed for reproduction operation using the lower digits of the addresses for fine retrieval. In another aspect of the present invention, there is provided a unique adapter which allows to carry out a dubbing operation between two 8 mm video units directly therethrough. In a further aspect of the present invention, there is provided a portable type video tape recorder system in which a VTR main body and a tuner are provided as separate entities and a commonly usable power supply unit may be mounted in either of the VTR main body or the tuner.

Abstract: A voltage converter circuit has an input terminal for receiving an input binary signal and a gate for generating an output binary signal corresponding to the input binary signal. An output signal from the gate is supplied to a first input terminal of an inverter through a transistor and further to a second input terminal of the inverter directly, so as to immediately stabilize the output signal from the voltage converter circuit. The inverter inverts the input signal to a higher-voltage binary signal. When a voltage level of the higher-voltage binary signal reaches a given voltage level while the voltage level of the higher-voltage binary signal changes, a feedback circuit is operated to set the input signal supplied to the first input terminal of the inverter at a higher voltage.

Abstract: A semiconductor nonvolatile read only memory device has a voltage applying circuit which sets all word lines at ground potential in a stand-by mode and sets only a selected word line at a high level in an active mode. The word lines are connected to the gates of semiconductor nonvolatile memory transistors. Each of the memory transistors has the source (or drain) grounded and the drain (or source) connected to output lines. In a stand-by mode, the voltage applying circuit keeps all the word lines at ground potential. In an active mode, the voltage applying circuit applies a high level voltage only to the selected word line. The memory transistor connected to the selected word line produces data of "0" or "1" to the output line.