Abstract: A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.

Abstract: A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.

Abstract: A method for manufacturing a thin film transistor array panel, including: sequentially forming a first silicon layer, a second silicon layer, a lower metal layer, and an upper metal layer on a gate insulating layer and a gate line; forming a first film pattern on the upper metal layer; forming a first lower metal pattern and a first upper metal pattern that includes a protrusion, by etching the upper metal layer and the lower metal layer; forming first and second silicon patterns by etching the first and second silicon layers; forming a second film pattern by ashing the first film pattern; forming a second upper metal pattern by etching the first upper metal pattern; forming a data line and a thin film transistor by etching the first lower metal pattern and the first and second silicon patterns; and forming a passivation layer and a pixel electrode on the resultant.

Abstract: The present disclosure relates to laser processing and a laser processing apparatus for processing materials using laser. Processing performed after loading a wafer on a work stage and a laser processing apparatus for implementing such processing, among others, are disclosed. The laser processing includes loading a wafer on a work stage; determining the number of chips formed on the wafer loaded on the work stage, performing chip defect inspection and aligning the wafer while moving the work stage; measuring a height of a surface of the wafer loaded on the work stage using a displacement sensor; monitoring output power of a processing laser using a power meter; and shifting the work stage while irradiating a laser beam on the wafer to process the wafer.

Abstract: Exemplary embodiments of the present invention provide a metal wiring etchant. A metal wiring etchant according to an exemplary embodiment of the present invention includes ammonium persulfate, an organic acid, an ammonium salt, a fluorine-containing compound, a glycol-based compound, and an azole-based compound.

Abstract: An etchant includes about 0.1 percent by weight to about 30 percent by weight of ammonium persulfate (NH4)2S2O8, about 0.1 percent by weight to about 10 percent by weight of an inorganic acid, about 0.1 percent by weight to about 10 percent by weight of an acetate salt, about 0.01 percent by weight to about 5 percent by weight of a fluorine-containing compound, about 0.01 percent by weight to about 5 percent by weight of a sulfonic acid compound, about 0.01 percent by weight to about 2 percent by weight of an azole compound, and a remainder of water. Accordingly, the etchant may have high stability to maintain etching ability. Thus, manufacturing margins may be improved so that manufacturing costs may be reduced.

Abstract: An etchant includes about 0.1 percent by weight to about 30 percent by weight of ammonium persulfate (NH4)2S2O8, about 0.1 percent by weight to about 10 percent by weight of an inorganic acid, about 0.1 percent by weight to about 10 percent by weight of an acetate salt, about 0.01 percent by weight to about 5 percent by weight of a fluorine-containing compound, about 0.01 percent by weight to about 5 percent by weight of a sulfonic acid compound, about 0.01 percent by weight to about 2 percent by weight of an azole compound, and a remainder of water. Accordingly, the etchant may have high stability to maintain etching ability. Thus, manufacturing margins may be improved so that manufacturing costs may be reduced.

Abstract: An etchant includes about 0.1 percent by weight to about 30 percent by weight of ammonium persulfate (NH4)2S2O8, about 0.1 percent by weight to about 10 percent by weight of an inorganic acid, about 0.1 percent by weight to about 10 percent by weight of an acetate salt, about 0.01 percent by weight to about 5 percent by weight of a fluorine-containing compound, about 0.01 percent by weight to about 5 percent by weight of a sulfonic acid compound, about 0.01 percent by weight to about 2 percent by weight of an azole compound, and a remainder of water. Accordingly, the etchant may have high stability to maintain etching ability. Thus, manufacturing margins may be improved so that manufacturing costs may be reduced.

Abstract: A method for manufacturing a thin film transistor array panel, including: sequentially forming a first silicon layer, a second silicon layer, a lower metal layer, and an upper metal layer on a gate insulating layer and a gate line; forming a first film pattern on the upper metal layer; forming a first lower metal pattern and a first upper metal pattern that includes a protrusion, by etching the upper metal layer and the lower metal layer; forming first and second silicon patterns by etching the first and second silicon layers; forming a second film pattern by ashing the first film pattern; forming a second upper metal pattern by etching the first upper metal pattern; forming a data line and a thin film transistor by etching the first lower metal pattern and the first and second silicon patterns; and forming a passivation layer and a pixel electrode on the resultant.

Abstract: A thin film transistor array and method of manufacturing the same include a pixel electrode formed of a transparent conductive layer on a substrate, a gate line formed of the transparent conductive layer and an opaque conductive layer on the substrate, a gate electrode connected to the gate line and formed of the transparent conductive layer and an opaque conductive layer on the substrate, a gate insulating layer which covers the gate line and the gate electrode, a semiconductor layer formed on the gate insulating layer to overlap the gate electrode, a data line which intersects the gate line, a source electrode connected to the data line to overlap a part of the semiconductor layer, and a drain electrode connected to the pixel electrode to overlap a part of the semiconductor layer.

Abstract: An etchant composition that allows simplification and optimization of semiconductor manufacturing process is presented, along with a method of patterning a conductive layer using the etchant and a method of manufacturing a flat panel display using the etchant. The etchant includes nitric acid, phosphoric acid, acetic acid, and an acetate compound in addition to water.

Abstract: The present invention provides a stripping composition and a stripping method capable of easily stripping a color resist or an organic insulating film formed on a substrate to reuse the substrate when defects are found during a process of forming the color filter or organic insulating film on the substrate. In one embodiment, the stripping composition includes about 0.5 to about 45 wt % of hydroxide compound, about 10 to about 89 wt % of alkyleneglycolalkylether compound, about 5 to about 45 wt % of alkanolamine compound, and about 0.01 to about 5 wt % of inorganic salt compound. Advantageously, the stripping process can be performed without damaging a thin film transistor of a bottom substrate while removing the color resist or organic insulating film.

Abstract: A thin film transistor substrate and a method of manufacturing the thin film transistor substrate comprises forming a gate line and a data line intersecting each other with a gate insulating layer interposed and defining a pixel area on the substrate, a thin film transistor electrically connected to the gate line and the data line, and a stepped-structure occurring pattern overlapping at least one of the gate line and the data line; forming a passivation layer having a stepped-structure portion formed by the stepped-structure occurring pattern on the substrate; forming a photoresist pattern having a second stepped-structure portion corresponding to the stepped-structure portion on the passivation layer; patterning the passivation layer using the photoresist pattern as a mask; forming a transparent conductive layer on the substrate; and removing the photoresist pattern where the transparent conductive layer is covered by a stripper penetrating through the stepped-structure portion of the photoresist pattern an

Abstract: The present disclosure relates to laser processing and a laser processing apparatus for processing materials using laser. Processing performed after loading a wafer on a work stage and a laser processing apparatus for implementing such processing, among others, are disclosed. The laser processing includes loading a wafer on a work stage; determining the number of chips formed on the wafer loaded on the work stage, performing chip defect inspection and aligning the wafer while moving the work stage; measuring a height of a surface of the wafer loaded on the work stage using a displacement sensor; monitoring output power of a processing laser using a power meter; and shifting the work stage while irradiating a laser beam on the wafer to process the wafer.

Abstract: A display substrate includes an insulating substrate, a thin film transistor, a contact electrode, and a pixel electrode. The thin film transistor includes a control electrode, a semiconductor pattern, a first electrode, and a second electrode. The control electrode is on the insulating substrate. The semiconductor pattern is on the control electrode. The first electrode is on the semiconductor pattern. The second electrode is spaced apart from the first electrode on the semiconductor pattern. The contact electrode includes a contact portion and an undercut portion. The contact portion is electrically connected to the second electrode to partially expose the semiconductor pattern. The undercut portion is electrically connected to the contact portion to cover the semiconductor pattern. The pixel electrode is electrically connected to the second electrode through the contact portion of the contact electrode.

Abstract: A composition for removing a photoresist includes a) an amine compound having a cyclic amine and/or a diamine, b) a glycol ether compound, c) a corrosion inhibitor and d) a polar solvent. The composition further includes a stripping promoter. Further disclosed is a method of manufacturing an array substrate using the composition for removing a photoresist.

Abstract: A gate line includes a first seed layer formed on a base substrate and a first metal layer formed on the first seed layer. A first insulation layer is formed on the base substrate. A second insulation layer is formed on the base substrate. Here, a line trench is formed through the second insulation layer in a direction crossing the gate line. A data line includes a second seed layer formed below the line trench and a second metal layer formed in the line trench. A pixel electrode is formed in a pixel area of the base substrate. Therefore, a trench of a predetermined depth is formed using an insulation layer and a metal layer is formed through a plating method, so that a metal line having a sufficient thickness may be formed.

Abstract: An etchant composition that allows simplification and optimization of semiconductor manufacturing process is presented, along with a method of patterning a conductive layer using the etchant and a method of manufacturing a flat panel display using the etchant. The etchant includes nitric acid, phosphoric acid, acetic acid, and an acetate compound in addition to water.

Abstract: Exemplary embodiments of the present invention provide a metal wiring etchant. A metal wiring etchant according to an exemplary embodiment of the present invention includes ammonium persulfate, an organic acid, an ammonium salt, a fluorine-containing compound, a glycol-based compound, and an azole-based compound.

Abstract: The present invention provides a stripping composition and a stripping method capable of easily stripping a color resist or an organic insulating film formed on a substrate to reuse the substrate when defects are found during a process of forming the color filter or organic insulating film on the substrate. In one embodiment, the stripping composition includes about 0.5 to about 45 wt % of hydroxide compound, about 10 to about 89 wt % of alkyleneglycolalkylether compound, about 5 to about 45 wt % of alkanolamine compound, and about 0.01 to about 5 wt % of inorganic salt compound. Advantageously, the stripping process can be performed without damaging a thin film transistor of a bottom substrate while removing the color resist or organic insulating film.