Abstract: In one embodiment, an inline defect analysis method includes receiving geometric characteristics of individual defects and design data corresponding to the individual defects, determining which of the individual defects are likely to be nuisance defects using the geometric characteristics and the corresponding design data, and refraining from sampling the defects that are likely to be nuisance defects.

Abstract: In one embodiment, a method for predicting yield during the design stage includes receiving defectivity data identifying defects associated with previous wafer designs, and dividing the defects into systematic defects and random defects. For each design layout of a new wafer design, yield is predicted separately for the systematic defects and the random defects. A combined yield is then calculated based on the yield predicted for the systematic defects and the yield predicted for the random defects.

Abstract: In one embodiment, a method for predicting yield includes calculating a criticality factor (CF) for each of a plurality of defects detected in an inspection process step of a wafer, and determining a yield-loss contribution of the inspection process step to the final yield based on CFs of the plurality of defects and the yield model built for a relevant design. The yield-loss contribution of the inspection process step is then used to predict the final yield for the wafer.

Abstract: In one embodiment, an inline defect analysis method includes receiving geometric characteristics of individual defects and design data corresponding to the individual defects, determining which of the individual defects are likely to be nuisance defects using the geometric characteristics and the corresponding design data, and refraining from sampling the defects that are likely to be nuisance defects.

Abstract: In one embodiment, a method for predicting yield includes calculating a criticality factor (CF) for each of a plurality of defects detected in an inspection process step of a wafer, and determining a yield-loss contribution of the inspection process step to the final yield based on CFs of the plurality of defects and the yield model built for a relevant design. The yield-loss contribution of the inspection process step is then used to predict the final yield for the wafer.

Abstract: Embodiments of the present invention provide methods and apparatuses for determining factors for design consideration in yield analysis of semiconductor fabrication. In one embodiment, a computer-implemented method for determining factors for design consideration in yield analysis of semiconductor fabrication includes obtaining a geometric characteristic of a defect on a chip and obtaining design data of the chip, where the design data is associated with the defect. The method further includes determining a criticality factor of the defect based on the geometric characteristic and the design data, and outputting the criticality factor.

Abstract: In one embodiment, a method for predicting yield during the design stage includes receiving defectivity data identifying defects associated with previous wafer designs, and dividing the defects into systematic defects and random defects. For each design layout of a new wafer design, yield is predicted separately for the systematic defects and the random defects. A combined yield is then calculated based on the yield predicted for the systematic defects and the yield predicted for the random defects.