Patents by Inventor Sung-Gi HUR
Sung-Gi HUR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11901357Abstract: A semiconductor device including a substrate that includes first and second regions; a first active pattern on the first region, the first active pattern including first source/drain patterns and a first channel pattern between the first source/drain patterns; a second active pattern on the second region, the second active pattern including second source/drain patterns and a second channel pattern between the second source/drain patterns; and a first gate electrode on the first channel pattern and a second gate electrode on the second channel pattern, wherein a length of the first channel pattern is greater than a length of the second channel pattern, each of the first channel pattern and the second channel pattern includes a plurality of semiconductor patterns stacked on the substrate, and at least two semiconductor patterns of the first channel pattern are bent away from or toward a bottom surface of the substrate.Type: GrantFiled: July 20, 2021Date of Patent: February 13, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Junggun You, Sung Gi Hur, Sungil Park, Wooseok Park, Seungmin Song
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Publication number: 20230387237Abstract: Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.Type: ApplicationFiled: August 15, 2023Publication date: November 30, 2023Inventors: MYUNG GIL KANG, Dong Won Kim, Woo Seok Park, Keun Hwi Cho, Sung Gi Hur
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Patent number: 11769813Abstract: Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction different from the first direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.Type: GrantFiled: October 14, 2022Date of Patent: September 26, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Myung Gil Kang, Dong Won Kim, Woo Seok Park, Keun Hwi Cho, Sung Gi Hur
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Publication number: 20230112528Abstract: Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction different from the first direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.Type: ApplicationFiled: October 14, 2022Publication date: April 13, 2023Inventors: MYUNG GIL KANG, Dong Won KIM, Woo Seok PARK, Keun Hwi CHO, Sung Gi HUR
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Patent number: 11482606Abstract: Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction different from the first direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.Type: GrantFiled: March 23, 2021Date of Patent: October 25, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Myung Gil Kang, Dong Won Kim, Woo Seok Park, Keun Hwi Cho, Sung Gi Hur
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Publication number: 20220328496Abstract: A semiconductor device includes a first active pattern on a substrate, a pair of first source/drain patterns on the first active pattern and a first channel pattern between the pair of first source/drain patterns, wherein the first channel pattern includes a plurality of semiconductor patterns that are stacked and spaced apart from each other, a first gate electrode on the first channel pattern, a first gate cutting pattern that is adjacent to the first channel pattern and penetrates the first gate electrode, and a first residual pattern between the first gate cutting pattern and the first channel pattern. The first residual pattern covers an outermost sidewall of at least one semiconductor pattern of the plurality of semiconductor patterns of the first channel pattern. The first gate electrode includes, on an upper portion of the first gate electrode, a first extension that vertically overlaps the first residual pattern.Type: ApplicationFiled: December 3, 2021Publication date: October 13, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Myung Gil KANG, Seunghun LEE, Sangdeok KWON, Keun Hwi CHO, Sung Gi HUR
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Publication number: 20220157811Abstract: A semiconductor device including a substrate that includes first and second regions; a first active pattern on the first region, the first active pattern including first source/drain patterns and a first channel pattern between the first source/drain patterns; a second active pattern on the second region, the second active pattern including second source/drain patterns and a second channel pattern between the second source/drain patterns; and a first gate electrode on the first channel pattern and a second gate electrode on the second channel pattern, wherein a length of the first channel pattern is greater than a length of the second channel pattern, each of the first channel pattern and the second channel pattern includes a plurality of semiconductor patterns stacked on the substrate, and at least two semiconductor patterns of the first channel pattern are bent away from or toward a bottom surface of the substrate.Type: ApplicationFiled: July 20, 2021Publication date: May 19, 2022Inventors: Junggun YOU, Sung Gi HUR, Sungil PARK, Wooseok PARK, Seungmin SONG
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Publication number: 20220037495Abstract: Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction different from the first direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.Type: ApplicationFiled: March 23, 2021Publication date: February 3, 2022Inventors: MYUNG GIL KANG, DONG WON KIM, WOO SEOK PARK, KEUN HWI CHO, SUNG GI HUR
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Patent number: 10896955Abstract: A semiconductor device includes a substrate, an active region disposed on the substrate and extending in a first direction, a device isolation layer adjacent to the active region, a gate structure disposed in the active region, the gate structure extending in a second direction crossing the first direction, and covering a portion of the device isolation layer, a gate separation pattern contacting an end of the gate structure, and an impurity region disposed below the gate separation pattern and on the device isolation layer.Type: GrantFiled: May 2, 2019Date of Patent: January 19, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kangmook Lim, Sang Su Kim, Woo Seok Park, Sung Gi Hur
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Publication number: 20200135848Abstract: A semiconductor device includes a substrate, an active region disposed on the substrate and extending in a first direction, a device isolation layer adjacent to the active region, a gate structure disposed in the active region, the gate structure extending in a second direction crossing the first direction, and covering a portion of the device isolation layer, a gate separation pattern contacting an end of the gate structure, and an impurity region disposed below the gate separation pattern and on the device isolation layer.Type: ApplicationFiled: May 2, 2019Publication date: April 30, 2020Inventors: Kangmook Lim, Sang Su Kim, Woo Seok Park, Sung Gi Hur
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Patent number: 10177150Abstract: A method of fabricating a semiconductor device includes preparing a substrate including a first region and a second region, sequentially forming a first semiconductor layer and a second semiconductor layer on the first and second regions, patterning the first and second semiconductor layers to form a lower semiconductor pattern and an upper semiconductor pattern on each of the first and second regions, selectively removing the lower semiconductor pattern on the second region to form a gap region, and forming gate electrodes at the first and second regions, respectively.Type: GrantFiled: June 6, 2017Date of Patent: January 8, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Junggil Yang, Sangsu Kim, TaeYong Kwon, Sung Gi Hur
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Patent number: 9978835Abstract: A semiconductor device includes at least one nanowire that is disposed over a substrate, extends to be spaced apart from the substrate, and includes a channel region, a gate that surrounds at least a part of the channel region, and a gate dielectric film that is disposed between the channel region and the gate. A source/drain region that contacts one end of the at least one nanowire is formed in a semiconductor layer that extends from the substrate to the one end of the at least one nanowire. Insulating spacers are formed between the substrate and the at least one nanowire. The insulating spacers are disposed between the gate and the source/drain region and are formed of a material that is different from a material of the gate dielectric film.Type: GrantFiled: October 31, 2016Date of Patent: May 22, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-Gil Yang, Sang-Su Kim, Sung-Gi Hur
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Publication number: 20170271335Abstract: A method of fabricating a semiconductor device includes preparing a substrate including a first region and a second region, sequentially forming a first semiconductor layer and a second semiconductor layer on the first and second regions, patterning the first and second semiconductor layers to form a lower semiconductor pattern and an upper semiconductor pattern on each of the first and second regions, selectively removing the lower semiconductor pattern on the second region to form a gap region, and forming gate electrodes at the first and second regions, respectively.Type: ApplicationFiled: June 6, 2017Publication date: September 21, 2017Inventors: Junggil YANG, SANGSU KIM, TaeYong KWON, SUNG GI HUR
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Patent number: 9711506Abstract: A method of fabricating a semiconductor device includes preparing a substrate including a first region and a second region, sequentially forming a first semiconductor layer and a second semiconductor layer on the first and second regions, patterning the first and second semiconductor layers to form a lower semiconductor pattern and an upper semiconductor pattern on each of the first and second regions, selectively removing the lower semiconductor pattern on the second region to form a gap region, and forming gate electrodes at the first and second regions, respectively.Type: GrantFiled: August 29, 2016Date of Patent: July 18, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Junggil Yang, Sangsu Kim, TaeYong Kwon, Sung Gi Hur
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Publication number: 20170047402Abstract: A semiconductor device includes at least one nanowire that is disposed over a substrate, extends to be spaced apart from the substrate, and includes a channel region, a gate that surrounds at least a part of the channel region, and a gate dielectric film that is disposed between the channel region and the gate. A source/drain region that contacts one end of the at least one nanowire is formed in a semiconductor layer that extends from the substrate to the one end of the at least one nanowire. Insulating spacers are formed between the substrate and the at least one nanowire. The insulating spacers are disposed between the gate and the source/drain region and are formed of a material that is different from a material of the gate dielectric film.Type: ApplicationFiled: October 31, 2016Publication date: February 16, 2017Inventors: Jung-Gil YANG, Sang-Su KIM, Sung-Gi HUR
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Publication number: 20160372474Abstract: A method of fabricating a semiconductor device includes preparing a substrate including a first region and a second region, sequentially forming a first semiconductor layer and a second semiconductor layer on the first and second regions, patterning the first and second semiconductor layers to form a lower semiconductor pattern and an upper semiconductor pattern on each of the first and second regions, selectively removing the lower semiconductor pattern on the second region to form a gap region, and forming gate electrodes at the first and second regions, respectively.Type: ApplicationFiled: August 29, 2016Publication date: December 22, 2016Inventors: Junggil YANG, SANGSU KIM, TaeYong KWON, SUNG GI HUR
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Patent number: 9515147Abstract: A semiconductor device includes at least one nanowire that is disposed over a substrate, extends to be spaced apart from the substrate, and includes a channel region, a gate that surrounds at least a part of the channel region, and a gate dielectric film that is disposed between the channel region and the gate. A source/drain region that contacts one end of the at least one nanowire is formed in a semiconductor layer that extends from the substrate to the one end of the at least one nanowire. Insulating spacers are formed between the substrate and the at least one nanowire. The insulating spacers are disposed between the gate and the source/drain region and are formed of a material that is different from a material of the gate dielectric film.Type: GrantFiled: March 21, 2016Date of Patent: December 6, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-Gil Yang, Sang-Su Kim, Sung-Gi Hur
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Patent number: 9502531Abstract: A semiconductor device includes a substrate having a first region and a second region, a first MOS transistor including a first fin structure and a first gate electrode in the first region, the first fin structure having a first buffer pattern, a second buffer pattern, and a first channel pattern which are sequentially stacked on the substrate, and a second MOS transistor including a second fin structure and a second gate electrode in the second region, the second fin structure having a third buffer pattern and a second channel pattern which are sequentially stacked on the substrate. Related fabrication methods are also discussed.Type: GrantFiled: May 26, 2016Date of Patent: November 22, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Sung Gi Hur, TaeYong Kwon, Sangsu Kim, Jungdal Choi
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Patent number: 9466601Abstract: A semiconductor device includes a substrate including first and second regions, a first transistor provided on the first region to include a first channel region protruding from the substrate, and a second transistor provided on the second region to include a second channel region and a gate electrode extending between the substrate and the second channel region. The first channel region may include a lower semiconductor pattern containing a different material from the second channel region and an upper semiconductor pattern containing the same material as the second channel region.Type: GrantFiled: May 12, 2014Date of Patent: October 11, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Junggil Yang, Sangsu Kim, TaeYong Kwon, Sung Gi Hur
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Publication number: 20160268394Abstract: A semiconductor device includes a substrate having a first region and a second region, a first MOS transistor including a first fin structure and a first gate electrode in the first region, the first fin structure having a first buffer pattern, a second buffer pattern, and a first channel pattern which are sequentially stacked on the substrate, and a second MOS transistor including a second fin structure and a second gate electrode in the second region, the second fin structure having a third buffer pattern and a second channel pattern which are sequentially stacked on the substrate. Related fabrication methods are also discussed.Type: ApplicationFiled: May 26, 2016Publication date: September 15, 2016Inventors: Sung Gi Hur, TaeYong Kwon, Sangsu Kim, Jungdal Choi