Patents by Inventor Sung-Ho Youn

Sung-Ho Youn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7939379
    Abstract: A hybrid carrier and a method for making the same, wherein the hybrid carrier has a plurality of interconnection leads, so that a wire bondable semiconductor device or a flip chip die apparatus can be placed on the hybrid carrier, and is electrically connected to die paddle and bond fingers. Also, it is easy to dispose a semiconductor device on the hybrid carrier and easy to electrically bond the hybrid carrier and the semiconductor device. Therefore, the hybrid carrier and the method for making the same can be applied to an area array metal CSP easily, and the method is simple, so the production cost can be reduced.
    Type: Grant
    Filed: February 5, 2008
    Date of Patent: May 10, 2011
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Sung-Ho Youn, Hyeong-No Kim
  • Publication number: 20090194858
    Abstract: The present invention relates to a hybrid carrier and a method for making the same. The hybrid carrier has a plurality of interconnection leads, so that a wire bondable semiconductor device or a flip chip die apparatus can be placed on the hybrid carrier, and is electrically connected to die paddle and bond fingers. Also, it is easy to dispose a semiconductor device on the hybrid carrier and easy to electrically bond the hybrid carrier and the semiconductor device. Therefore, the hybrid carrier and the method for making the same can be applied to an area array metal CSP easily, and the method of the present invention is simple, so the production cost can be reduced.
    Type: Application
    Filed: February 5, 2008
    Publication date: August 6, 2009
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Sung-Ho Youn, Hyeong-No Kim
  • Publication number: 20090127682
    Abstract: A method of fabricating a chip package structure is provided. A metallic plate having a first surface, a second surface, and a first patterned metallic layer formed on the first surface thereof is provided. A half-etching process is performed to form first recesses on the first surface of the metallic plate, wherein leads are defined on the metallic plate by the first recesses. A first insulating material fills in each of the first recesses. A second patterned metallic layer is formed on the second surface of the metallic plate. A half-etching process is performed to form second recesses on the second surface of the metallic plate. The second recesses correspond to the first recesses, respectively, and expose the first insulating material inside the first recesses, such that the leads are electrically isolated from one another. A chip is placed on the metallic plate and electrically connected thereto.
    Type: Application
    Filed: November 16, 2007
    Publication date: May 21, 2009
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hyeongno Kim, Sung-Ho Youn
  • Patent number: 7208341
    Abstract: A method for manufacturing a printed circuit board includes: forming inner circuit patterns in an insulating material in multi-layers, forming a plurality of through holes at certain portions of the insulating material, and forming an outer circuit pattern which is electrically connected to the inner circuit pattern, at an inner circumferential surface of the through hole and the surface of the insulating material, and a terminal portion; forming a first photo solder resist layer at an entire surface of the insulating material and an entire surface of the outer circuit pattern, and exposing the terminal portion by removing a specific portion of the first photo solder resist layer; abrading the surface of the first photo solder resist layer; printing a second photo solder resist layer at the surface of the first photo solder resist layer, and exposing the terminal portion to the outside by removing a specific portion of the second photo solder resist layer; and forming a pad portion by plating the surface of t
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: April 24, 2007
    Assignee: LG Electronics Inc.
    Inventors: Kwang-Tae Lee, Sung-Gue Lee, Sang-Hyuck Nam, Sung-Ho Youn, Young-Kyu Lee
  • Publication number: 20040241904
    Abstract: A method for manufacturing a printed circuit board includes: forming inner circuit patterns in an insulating material in multi-layers, forming a plurality of through holes at certain portions of the insulating material, and forming an outer circuit pattern which is electrically connected to the inner circuit pattern, at an inner circumferential surface of the through hole and the surface of the insulating material, and a terminal portion; forming a first photo solder resist layer at an entire surface of the insulating material and an entire surface of the outer circuit pattern, and exposing the terminal portion by removing a specific portion of the first photo solder resist layer; abrading the surface of the first photo solder resist layer; printing a second photo solder resist layer at the surface of the first photo solder resist layer, and exposing the terminal portion to the outside by removing a specific portion of the second photo solder resist layer; and forming a pad portion by plating the surface of t
    Type: Application
    Filed: May 28, 2004
    Publication date: December 2, 2004
    Applicant: LG Electronics Inc.
    Inventors: Kwang-Tae Lee, Sung-Gue Lee, Sang-Hyuck Nam, Sung-Ho Youn, Young-Kyu Lee
  • Patent number: D667800
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: September 25, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung Hwan Choi, Jung Kyu Park, Young Sik Jeong, Jin Mo Kim, Sung Ho Youn, Man Ki Hong, Churl Wung Shin, Tae Heon Han