Abstract: Provided are nonvolatile memory devices and methods of operating thereof. The nonvolatile memory devices include: dummy cells connected to a dummy bit line; and a dummy bit line bias circuit providing a dummy bit line voltage to the dummy bit line during a program operation, wherein, due to the dummy bit line voltage, at least one of the dummy cells is programmed with a threshold voltage lower than the top programmed state and higher than an erased state during the program operation.

Abstract: A nonvolatile memory device and method of manufacturing the same are provided. In the nonvolatile memory device, a blocking insulation layer is provided between a trap insulation layer and a gate electrode. A fixed charge layer spaced apart from the gate electrode is provided in the blocking insulation layer. Accordingly, the reliability of the nonvolatile memory device is improved.

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first dielectric pattern, a data storage pattern and a second dielectric pattern, which are sequentially stacked on a semiconductor substrate. A first conductive pattern is provided on the second dielectric pattern. A second conductive pattern having a greater width than the first conductive pattern is provided on the first conductive pattern.

Abstract: The present invention relates to polymer patterns of various shapes formed using modifications of means and methods used in the prior lithography process, and the metal film patterns, metal patterns and plastic molds using the polymer patterns, as well as methods of forming these patterns and molds. The method of forming the polymer patterns comprises the steps of: (a) depositing a photosensitive polymer on the substrate to form a polymer film; (b) placing a photomask on the polymer film; and (c) irradiating the polymer film with a light moving in random direction through the photomask, so as to form at least one pattern which is concave from the surface of the polymer film in a direction perpendicular to the substrate and extends in a direction parallel to the substrate. The inventive polymer patterns have at least one pattern which is concave from the surface of the polymer film in a direction perpendicular to the substrate and extends in a direction parallel to the substrate.

Abstract: A non-volatile memory device may include a semiconductor substrate and an isolation layer on the semiconductor substrate wherein the isolation layer defines an active region of the semiconductor substrate. A tunnel insulation layer may be provided on the active region of the semiconductor substrate, and a charge storage pattern may be provided on the tunnel insulation layer. An interface layer pattern may be provided on the charge storage pattern, and a blocking insulation pattern may be provided on the interface layer pattern. Moreover, the block insulation pattern may include a high-k dielectric material, and the interface layer pattern and the blocking insulation pattern may include different materials. A control gate electrode may be provided on the blocking insulating layer so that the blocking insulation pattern is between the interface layer pattern and the control gate electrode. Related methods are also discussed.

Abstract: Provided is a method for forming metal interconnect only in desired regions of a semiconductor device based on selective damascene using an insulation material against plating to form the metal interconnect without a Chemical Mechanical Polishing (CMP) or an additional lithography process. The selective damascene is stable and effective in the respect of cost and simplifies the semiconductor interconnect forming process.

Abstract: Disclosed is a method of fabricating an MOS transistor. The method comprises the following steps of: forming a gate pattern having a gate insulation film, main gate and a capping layer which are sequentially layered on a p-type semiconductor substrate; forming an isolating insulation film on the whole surface of a resultant structure having the gate pattern; forming a material layer for side gate on the isolating insulation film, the material layer having a work function smaller than those of the semiconductor substrate and the main gate; anisotropically etching the material layer for side gate and the isolating insulation film till the semiconductor substrate and the capping layer are exposed to form an isolating insulation pattern and side gate; respectively forming an n-type source/drain; and forming a conductive film pattern on the resultant structure, the conductive film electrically connecting the source to the adjacent side gate or the drain to the adjacent side gate.