Patents by Inventor Sung-In Jung

Sung-In Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190177522
    Abstract: The present invention relates to a method of preparing a thermoplastic resin, a method of preparing a thermoplastic resin composition including the same, and a method of manufacturing an injection-molded article using the thermoplastic resin composition. By using a mixture of molecular weight modifiers having different reactivities according to the present invention, coagulation may be performed using a small amount of coagulant, productivity may be increased, and a molded article, which is manufactured using a thermoplastic resin, having excellent appearance characteristics along with superior mechanical strength, processability, or the like may be provided.
    Type: Application
    Filed: November 15, 2017
    Publication date: June 13, 2019
    Inventors: Jong Beom KIM, Joo Byung CHAI, Yu Sung JUNG, Chang Sull KIM, Eun Seon PARK, Tae Young JEON, Young Min KIM
  • Publication number: 20190181539
    Abstract: An electronic device includes a housing comprising a first surface, a second surface, and a side surface, a touch screen display positioned inside the housing, wherein the display comprises a display panel and a touch panel that is separated from or integrated with the display panel, a conductive member (conductor) forming at least a portion of the side surface, at least one substantially transparent conductive pattern that is integrated into the display, a ground member (ground) interposed between the first surface and the second surface, a wireless communication circuit including a port electrically coupled to the conductive member, and a processor electrically coupled to the display and the wireless communication circuit. The substantially transparent conductive pattern is electrically coupled to the port of the wireless communication circuit and/or the ground member.
    Type: Application
    Filed: February 19, 2019
    Publication date: June 13, 2019
    Inventors: Ki Huk LEE, Moo Young KIM, Min Sik KIM, Ho Saeng KIM, Dong Ryul SHIN, Min Sung LEE, Song Hee JUNG, Jae Bong CHUN, Seung Jun HYUN
  • Publication number: 20190180881
    Abstract: The present invention relates to a non-invasive prenatal testing method and, more particularly, to a method for enhancing the sensitivity and accuracy of non-invasive prenatal testing by applying multi-dimensional threshold values based on multiple Z-scores. Designed to reduce false-positive and false-negative possibility by applying two or more Z-score threshold values to aneuploidy detection for one chromosome, the non-invasive prenatal testing method according to the present invention exhibits the effect of obtaining a more sensitive and more accurate test result. Further, the method can minimize test errors in spite of using a small number of nucleotide sequence fragments, with the resultant effect of reducing an experiment cost and thus expensive testing cost and rapidly performing testing with a low expense.
    Type: Application
    Filed: June 9, 2017
    Publication date: June 13, 2019
    Applicant: EONE DIAGNOMICS GENOME CENTER CO., LTD
    Inventors: Min Seob LEE, Shang Cheol SHIN, Sung Hoon LEE, Hyuk Jung KWON
  • Patent number: 10319858
    Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a lower fin that protrudes from a substrate and extends in a first direction, an oxide film the lower fin, an upper fin that protrudes from the oxide film and that is spaced apart from the lower fin at a position corresponding to the lower fin, and a gate structure the upper fin that extends in a second direction to intersect the upper fin, wherein germanium (Ge) is included in a portion of the oxide film located between the lower fin and the upper fin.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: June 11, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Min Kim, Kyung-Seok Oh, Cheol Kim, Heon-Jong Shin, Jong-Ryeol Yoo, Hyun-Jung Lee, Seong-Hoon Jeong
  • Patent number: 10319526
    Abstract: A thin-film capacitor includes a body having a plurality of dielectric layers and first and second electrode layers alternately stacked on a substrate, first and second electrode pads disposed on one surface of the body, a plurality of vias having a multistage shape being disposed in the body, a first via of the plurality of vias connects the first electrode layer to the first electrode pad, and penetrates from the surface of the body to a first lowermost electrode layer adjacent the substrate, a second via of the plurality of vias connects the second electrode layer to the second electrode pad, and penetrates from the surface of the body to a second lowermost electrode layer adjacent the substrate and an upper surface of the first electrode layer is exposed in the first via, and an upper surface of the second electrode layer is exposed in the second via.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: June 11, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Hyun Ho Shin, Yun Sung Kang, Seung Mo Lim, Kyo Yeol Lee, Dong Joon Oh, Woong Do Jung, Ho Phil Jung, Hai Joon Lee
  • Patent number: 10318832
    Abstract: A method and apparatus for authenticating a user using a vein pattern are provided that project a near infrared (NIR) ray toward a skin of the user using a light emitting diode (LED), where the user is adjacent to a terminal including the LED. An image sensor receives a light reflected by the skin, generates a vein pattern of the skin based on an image generated using the received light, and authenticates the user as a registered user of a pre-stored vein pattern when the generated vein pattern matches the pre-stored vein pattern.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: June 11, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jungsoon Shin, Namjoon Kim, Joonah Park, Soochul Lim, Jaehyuk Choi, Tae-Sung Jung
  • Patent number: 10319522
    Abstract: A multilayer ceramic capacitor includes: a capacitance layer including dielectric layers and first and second internal electrodes disposed with respective dielectric layers interposed therebetween; a protection layer disposed on one surface of the capacitance layer; an alpha connection electrode provided in an alpha via penetrating through the protection layer; and a beta connection electrode provided in a beta via penetrating through the capacitance layer and connected to the alpha via. The alpha via has a diameter greater than that of the beta via.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: June 11, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Taek Jung Lee, Hyo Youn Lee, Seung Woo Song, Jong Pil Lee, Sung Kwon An
  • Publication number: 20190170788
    Abstract: A scanning probe inspector comprises: a probe that includes a cantilever and a tip whose length corresponds to a depth of a trench that is formed in a wafer; a trench detector that acquires location information of the trench using the probe, where the location information includes depth information of the trench; a controller that inserts the tip into a first point where there exists a trench based on the location information of the trench, and moves the tip through the trench using the location information of the trench; and a defect detector that detects a presence of a defect in a sidewall of the trench as the tip is moved through the trench.
    Type: Application
    Filed: September 13, 2018
    Publication date: June 6, 2019
    Inventors: Duck Mahn Oh, Sung Yoon Ryu, Young Hoon Sohn, Chung Sam Jun, Yun Jung Jee
  • Publication number: 20190172840
    Abstract: In some embodiments, 3-dimensional semiconductor memory device includes a semiconductor substrate extending horizontally in a first direction and a second direction crossing the first direction. A stacked memory cell array is formed on the semiconductor substrate. The memory device further includes a separation pattern including a plurality of separation lines extending in the first direction and arranged in the second direction, and dividing the stacked memory cell array into a plurality of memory cell structures extending in the first direction and arranged in the second direction. An upper insulating layer is formed above the plurality of memory cell structures and separation lines, and a passivation layer is formed above the upper insulating layer. The passivation layer includes a plurality of first regions having a first vertical thickness. A plurality of gap regions in the passivation layer are formed between the plurality of first regions.
    Type: Application
    Filed: September 21, 2018
    Publication date: June 6, 2019
    Inventors: Min Sung SONG, Heung Jin JOO, Kwan Yong KIM, Jin Woo PARK, Du Heon SONG, He Jueng LEE, Myung Ho JUNG
  • Publication number: 20190172648
    Abstract: A capacitor component includes a plurality of unit laminates, each comprising a body with a stacked structure including a plurality of internal electrodes and connection electrodes that extend in a stacking direction of the body and electrically connect to the plurality of internal electrodes, and pad portions between adjacent unit laminates to electrically connect the respective connection electrodes of the unit laminates above and below the pad portions to each other.
    Type: Application
    Filed: February 12, 2019
    Publication date: June 6, 2019
    Inventors: Taek Jung LEE, Jin Kyung JOO, Hyo Youn LEE, Won Young LEE, Sung Kwon AN, Jae Yeol CHOI, Jin Man JUNG
  • Publication number: 20190172645
    Abstract: A multilayer capacitor and a board having the same provide high capacitance and low equivalent series inductance (ESL). The multilayer capacitor includes a capacitor body including an active region, including first and second internal electrodes, and first and second cover regions. Third and fourth internal electrodes are alternately disposed in the cover region adjacent to a mounting surface. First and second external electrodes respectively contact the first and second internal electrodes to provide capacitance. First and second via electrodes are disposed in the cover region, where the first via electrode connects the third internal electrode and a first band portion of the first external electrode to each other, and where the second via electrode connects the fourth internal electrode and a second band portion of the second external electrode to each other.
    Type: Application
    Filed: February 8, 2019
    Publication date: June 6, 2019
    Inventors: Jong Pil LEE, Hyo Youn LEE, Sung Kwon AN, Seung Woo SONG, Taek Jung LEE, Jin Kyung JOO
  • Patent number: 10312074
    Abstract: A method of producing a layer structure includes forming a first organic layer by applying a first composition including an organic compound on a substrate having a plurality of patterns, applying a solvent on the first organic layer to remove a part of the first organic layer, and applying a second composition including an organic compound on a remaining part of the first organic layer and forming a second organic layer through a curing process.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: June 4, 2019
    Assignee: SAMSUNG SDI CO., LTD.
    Inventors: Min-Soo Kim, Hyun-Ji Song, Sun-Hae Kang, Sung-Min Kim, Sung-Hwan Kim, Young-Min Kim, Yun-Jun Kim, Hea-Jung Kim, Youn-Hee Nam, Jae-Yeol Baek, Byeri Yoon, Yong-Woon Yoon, Chung-Heon Lee, Seulgi Jeong, Yeon-Hee Jo, Seung-Hee Hong, Sun-Min Hwang, Won-Jong Hwang, Songse Yi, MyeongKoo Kim, Naery Yu
  • Patent number: 10307768
    Abstract: The present invention relates to a CLC and operation method thereof equipped with a loop seal separator using magnetic oxygen carrier particles and a magnetic separator. And more particularly, the present invention relates to a loop seal separator using magnetic oxygen carrier particles and a magnetic separator, wherein the loop seal separator comprises a duct into which the ash and magnetic oxygen carrier particles, discharged from a reducer, flow; a magnetic separator to separate the ash from the magnetic oxygen carrier particles, flowing into the duct, by magnetic material; an ash discharge pipe to discharge the ash, separated by the magnetic separator; and an oxygen-carrier-particle discharge pipe to encourage the magnetic oxygen carrier particles, separated by the magnetic separator, to flow into an oxidizer.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: June 4, 2019
    Assignee: Korea Institute of Energy Research
    Inventors: Ho-Jung Ryu, Keun-hee Han, Gyoung-tae Jin, Chang-keun Yi, Do-won Shun, Jae-hyeon Park, Dal-hee Bae, Sung-ho Jo, Seung-yong Lee, Young Cheol Park, Jong-ho Moon, Do Yeon Lee, Hyo Jin Lee, Dong-ho Lee, Jeom In Baek
  • Patent number: 10313801
    Abstract: Provided is a sound output apparatus including: a housing having a housing space therein; a first sound output unit provided inside the housing; and a second sound output unit provided in the housing and spaced a predetermined distance from the first sound output unit.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: June 4, 2019
    Assignee: MODA-INNOCHIPS CO., LTD.
    Inventors: Sung Cheol Park, Sang Hun Park, In Seob Jung
  • Publication number: 20190161861
    Abstract: Disclosed is a substrate processing apparatus and method which facilitates to sequentially or repetitively carry out a thin film deposition process and a surface treatment process inside one process space, wherein the substrate processing apparatus comprises a process chamber for providing a process space; a substrate supporter for supporting at least one of substrates and moving the supported substrate in a predetermined direction; a chamber lid confronting the substrate supporter; and a gas distributor for spatially separating process gas for depositing a thin film on the substrate from a surface treatment gas for performing a surface treatment of the thin film, and locally distributing the process gas and the surface treatment gas on the substrate supporter, wherein the gas distributor confronting the substrate supporter is provided in the chamber lid.
    Type: Application
    Filed: January 31, 2019
    Publication date: May 30, 2019
    Inventors: Jae Chan KWAK, Sung Kyu KANG, Hun JUNG, Byoung Ha CHO
  • Publication number: 20190164976
    Abstract: A semiconductor memory device according to an example embodiment of the present inventive concept may include: a plurality of lower electrodes located on a substrate and spaced apart from one another; and an etch stop pattern located on the substrate and surrounding at least a part of each of the plurality of lower electrodes, in which the etch stop pattern includes: a first etch stop pattern including carbon; and a second etch stop pattern located on the first etch stop pattern and including a material different from a material of the first etch stop pattern.
    Type: Application
    Filed: June 11, 2018
    Publication date: May 30, 2019
    Inventors: Hui-jung Kim, Bong-soo Kim, Sung-hee Han, Yoo-sang Hwang
  • Patent number: 10303686
    Abstract: In one aspect there is a method. The method may include associating a query received from an application with a hint, wherein the hint modifies an execution of the query. The method may further include an optimizer to compile the query according to the hint to produce a second query plan. When no hint is associated with the query, the optimizer may produce a first query plan. The method may further include storing the hint in a persistent table to enable state preservation during a database restart or binary upgrade, and/or executing the query using the second query plan.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: May 28, 2019
    Assignee: SAP SE
    Inventors: Jane Jung Lee, Taehyung Lee, Jiyoung Yoo, Sung Heun Wi, Ki Hong Kim
  • Patent number: 10304807
    Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a first semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface; a first encapsulant encapsulating at least portions of the first interconnection member and the first semiconductor chip; a second interconnection member disposed on the first interconnection member and the first semiconductor chip; a second semiconductor chip disposed on the first encapsulant and having an active surface having connection pads disposed thereon; and a second encapsulant encapsulating at least portions of the second semiconductor chip.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: May 28, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Dae Hyun Park, Eun Jung Jo, Sung Won Jeong, Han Kim, Mi Ja Han
  • Publication number: 20190153390
    Abstract: The present invention relates to a composition for inducing dendritic cell maturation and a method for maturing dendritic cells. More particularly, the present invention relates to a composition including a fusion protein of Rv2299c and ESAT-6, both derived from M. tuberculosis, as an active ingredient for inducing dendritic cell maturation, and a method for differentiating immature dendritic cells into dendritic cells by using the same. The method of the present invention can increase a dendritic cell immune response in the body.
    Type: Application
    Filed: November 29, 2018
    Publication date: May 23, 2019
    Inventors: Hwa-Jung Kim, Han-Gyu Choi, Sung Jae Shin
  • Publication number: 20190151465
    Abstract: The present invention relates to antibody-drug conjugates (ADCs) wherein a plurality of active agents are conjugated to an antibody through at least one branched linker. The branched linker may comprise a branching unit, and two active agents are coupled to the branching unit through a secondary linker and the branching unit is coupled to the antibody by a primary linker. The active agents may be the same or different. In certain such embodiments, two or more such branched linkers are conjugated to the antibody, e.g., 2-4 branched linkers, which may each be coupled to a different C-terminal cysteine of a heavy or light chain of the antibody. The branched linker may comprise one active agent coupled to the branching unit by a first branch and a second branch that comprises a polyethylene glycol moiety coupled to the branching unit. In certain such embodiments, two or more such branched linkers are conjugated to the antibody, e.g.
    Type: Application
    Filed: November 23, 2016
    Publication date: May 23, 2019
    Inventors: Yong Zu Kim, Yeong Soo Oh, Jeiwook Chae, Ho Young Song, Chul-Woong Chung, Yun Hee Park, Hyo Jung Choi, Kyung Eun Park, Hyoungrae Kim, Jinyeong Kim, Ji Young Min, Sung Min Kim, Byung Soo Lee, Dong Hyun Woo, Ji Eun Jung, Su In Lee