Abstract: A semiconductor package according to an embodiment includes a first insulating layer; and a first through electrode part passing through the first insulating layer and having a shape elongated in a first direction; wherein the first through electrode part includes a plurality of first through electrodes spaced apart from each other in a second direction perpendicular to the first direction and a thickness direction; wherein at least one of the plurality of first through electrodes includes a first sub through electrode and a second sub through electrode spaced apart from each other in the first direction; and wherein at least one of the first sub through electrode and the second sub through electrode has a width in the first direction greater than a width in the second direction.

Abstract: A multichannel manifold cold plate with microchannels for cooling electronics. A main inlet is on a side of the microchannels opposite the cold plate and includes inlet channels with nozzles adjacent the microchannels. A main outlet is on a side of the microchannels opposite the cold plate and includes outlet channels with nozzles adjacent the microchannels. The inlet channels are interleaved with the outlet channels. In operation, the main inlet delivers a cooling fluid to the cold plate microchannels via the inlet channels and nozzles, and the main outlet receives the cooling fluid from the microchannels via the outlet channels and nozzles. This configuration provides a cooling fluid distribution pattern for efficient cooling of the electronics.

Abstract: Proposed is a system based on the Internet of Media Things (IoMT). The system may include at least one first sensor configured to perform a predetermined function in a target space or region, and a second sensor based on at least one of video or audio. The system may also include a first analysis processor configured to generate first analysis data of a set mission within the target space or region based on first data sensed by the first sensor. The system may further include a second analysis processor configured to generate second analysis data for a set mission within the target space or region based on second data sensed by the second sensor. The system may further include storage configured to store the sensed first data and second data and the first and second analysis data based on the identifier.

Abstract: Disclosed herein are an apparatus and method for updating an Internet-based malware detection engine using virtual machine scaling. The method may include creating a scaling group and an update group set based on a first virtual machine image, creating a second virtual machine image for a running virtual machine in response to occurrence of a snapshot event in the virtual update group run based on the first virtual machine image, modifying the scale-out image of the scaling group to the second virtual machine image, updating the scaling group by triggering a scale-out event and a scale-in event in the scaling group in response to occurrence of an update event, and modifying the scale-in image of the scaling group to the second virtual machine image.

Abstract: An aspect of the present invention provides a metal pillar in a columnar shape formed by cutting a metal wire to a predetermined length. The metal pillar has a burr length of 0.1 to 0.5 ?m on the cutting surface and provide a connecting pillar that has a solder layer on at least one area of the outer surface of the metal pillar, which comprises Sn, Cu, and Ag.

Abstract: An aspect of the present invention provides a metal pillar in a columnar shape formed by cutting a metal wire to a predetermined length. The metal pillar has a burr length of 0.1 to 0.5 ?m on the cutting surface, an electrical conductivity of 11 to 101% IACS, and a Vickers hardness of 150 to 300 HV.

Abstract: Provided is a peptide composition for preventing or treating Alzheimer's dementia. A peptide or a salt substituent thereof according to the presently claimed subject matter exhibits effects such as suppression of LPS-mediated cytokine production, suppression of LPS-induced neuroinflammation, amelioration of cognitive impairment, suppression of beta amyloid or tau protein aggregation, and suppression of neuronal loss. The polypeptide or the salt substituent thereof can permeate the blood-brain barrier, and thus, is expected to be usefully used for preventing or treating Alzheimer's dementia.

Abstract: A complementary thin film transistor (TFT) includes a substrate and a first TFT and a second TFT disposed on the substrate, wherein a first conductive semiconductor layer of the first TFT and a second gate electrode layer of the second TFT are disposed in the same layer and include the same material.

Abstract: A multilayer capacitor includes a body including a dielectric layer and a plurality of internal electrodes stacked on each other with the dielectric layer interposed therebetween; and external electrodes disposed externally on the body, and respectively including a first layer connected to the internal electrode and a second layer covering the first layer, wherein the first layer includes a metal particle including an element A, an oxide of an element Z, formed on the metal particle, and an A-Z intermetallic compound phase, and here, the element Z has a higher ionization tendency than the element A.

Abstract: A display device including: a substrate; an active layer disposed on the substrate and including active patterns; a first conductive layer disposed on the active layer; a second conductive layer disposed on the first conductive layer and including a data line; a third conductive layer disposed on the second conductive layer; and a light-emitting element disposed on the third conductive layer, wherein the first conductive layer includes a scan line, a first voltage line, and a second voltage line, the third conductive layer includes a third voltage line connected to the first voltage line and a fourth voltage line connected to the second voltage line, the first voltage line and the second voltage line extend in a first direction, the third voltage line and the fourth voltage line extend in a second direction, and the third voltage line and the fourth voltage line are alternately arranged in the first direction.

Abstract: Purge diffusers for use in systems for transporting substrates include: i) a purge diffuser core having an internal purge gas channel, one or more diffuser ports and an outer surface; ii) filter media secured to the outer surface of the purge diffuser core; and iii) a purge port connector for mounting the purge diffuser to a purge port of a substrate container for transporting substrates. The purge diffuser core may be a unitary article, may be formed by injection molding, and may include diverters internal to the internal purge gas channel.

Abstract: Disclosed are a system and method for analyzing a stool image, which derive the state of the large intestine of a user by analyzing a stool image by using a pre-trained deep learning model. The system for analyzing a stool image may include an input unit configured to receive stool images of a user, a data set generation unit configured to generate a data set by grouping the stool images in chronological order, an analysis unit configured to derive information on a stool state of the user or information on a state of the large intestine of the user by analyzing the data set, and an output unit configured to output the information on the stool state or the information on the state of the large intestine. The endoscopic activity of ulcerative colitis can be predicted from a camera image of stool even without performing a colonoscopy.

Abstract: A semiconductor device comprises a first gate structure extending in a first direction and including a first gate electrode and a first gate capping pattern, a second gate structure spaced apart from the first gate structure and extending in the first direction, and including a second gate electrode and a second gate capping pattern, an active pattern extending in a second direction, the active pattern below the second gate structure, an epitaxial pattern on one side of the second gate structure and on the active pattern, a gate contact connected to the first gate electrode, and a node contact connected to the second gate electrode and to the epitaxial pattern. An upper surface of the gate contact is at a same level as the first gate capping pattern, and an upper surface of the node contact is lower than the upper surface of the first gate capping pattern.

Abstract: A semiconductor device includes: a base substrate; a first interlayer insulating layer disposed on the base substrate; a power rail disposed inside the first interlayer insulating layer; an active pattern extended in a first horizontal direction and disposed on the first interlayer insulating layer; a gate electrode extended in a second horizontal direction different from the first horizontal direction and disposed on the active pattern; a gate cut extended in the first horizontal direction and disposed on the power rail, wherein the gate cut separates the gate electrode; and a power rail via disposed inside the gate cut, wherein the power rail via is overlapped by the power rail.

Abstract: A substrate processing apparatus including a process chamber; a susceptor in the process chamber; and an inner edge ring and an outer edge ring on the susceptor, wherein the inner edge ring includes a semiconductor, the outer edge ring includes an insulator, an upper surface of the outer edge ring is at a higher level than an upper surface of the inner edge ring, and the outer edge ring has an overhang extending onto the inner edge ring.

Abstract: A semiconductor device includes a first active pattern extending lengthwise along a first direction and a second active pattern extending lengthwise along the first direction and spaced apart from the first active pattern in the first direction. The device also includes a field insulating film between the first active pattern and the second active pattern. An upper surface of the field insulating film is lower than or coplanar with upper surfaces of the first and second active patterns. The device further includes an element isolation structure in an isolation trench in the first active pattern and the field insulating film. An upper surface of the element isolation structure is higher than the upper surfaces of the first and second active patterns.

Abstract: A method of manufacturing a semiconductor chip includes forming a first stack by alternately stacking first material layers and second material layers over a semiconductor substrate, forming a first trench penetrating the first stack, and forming a first stress concentration portion by forming a second stack over the first stack.

Abstract: Proposed is a vacuum carrier. The vacuum carrier includes a vacuum base having vacuum passages (20VP and 30VP) formed therein, the vacuum passages (20VP and 30VP) being connected to vacuum suction holes (24 and 34), and includes a vacuum unit configured to form a vacuum by suctioning air from the vacuum passages (20VP and 30VP) inside the vacuum base. Further, the vacuum unit includes a vacuum filling block (51) having suction ports connected to a vacuum apparatus, and includes a movement driving apparatus configured to move the vacuum filling block (51) such that the suction ports of the vacuum filling block (51) are connected to the vacuum passages (20VP and 30VP) inside the vacuum base.

Abstract: Disclosed herein are an apparatus for detecting unknown malware using a variable-length operation code (opcode) and a method using the apparatus. The method includes collecting opcode information from a detection target, generating a multi-pixel image having a variable length by performing feature engineering on the opcode information; and detecting unknown malware by inputting the multi-pixel image to a deep-learning model based on AI.

Abstract: A substrate processing apparatus including a process chamber; a susceptor in the process chamber; and an inner edge ring and an outer edge ring on the susceptor, wherein the inner edge ring includes a semiconductor, the outer edge ring includes an insulator, an upper surface of the outer edge ring is at a higher level than an upper surface of the inner edge ring, and the outer edge ring has an overhang extending onto the inner edge ring.