Patents by Inventor Sung Jin Whang

Sung Jin Whang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9515074
    Abstract: A three-dimensional (3-D) non-volatile memory device includes a plurality of word line structures extended in parallel and including a plurality of interlayer dielectric layers and a plurality of word lines that are alternately stacked over a substrate, a plurality of channels protruding from the substrate configured to penetrate the plurality of interlayer dielectric layers and the plurality of word lines, and an air gap formed between the plurality of word line structures.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: December 6, 2016
    Assignee: SK Hynix Inc.
    Inventors: Sung Jin Whang, Ki Hong Lee
  • Patent number: 9466733
    Abstract: This technology relates to a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode over a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each connected with the pipe channel layer and extended in a direction substantially perpendicular to the substrate, a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers, and metal silicide layers configured to be in contact with the pipe connection gate electrode. The electric resistance of the pipe connection gate electrode may be greatly reduced without deteriorating the characteristics of the memory layers by forming the metal silicide layers coming in contact with the pipe connection gate electrode.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: October 11, 2016
    Assignee: SK Hynix Inc.
    Inventors: Min-Soo Kim, Young-Jin Lee, Sung-Jin Whang
  • Patent number: 9466609
    Abstract: The device includes plural control gates stacked on a substrate, plural first channels, configured to penetrate the control gates, and plural memory layer patterns, each located between the control gate and the first channel, configured to respectively surround the first channel, wherein the memory layer patterns are isolated from one another.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: October 11, 2016
    Assignee: SK Hynix Inc.
    Inventors: Min Soo Kim, Dong Sun Sheen, Young Jin Lee, Jin Hae Choi, Joo Hee Han, Sung Jin Whang
  • Patent number: 9385135
    Abstract: A nonvolatile memory device includes a substrate; a channel layer projecting from a surface of the substrate, in a direction perpendicular to the surface; a tunnel dielectric layer surrounding the channel layer; a plurality of interlayer dielectric layers and a plurality of control gate electrodes alternately formed along the channel layer; floating gate electrodes interposed between the tunnel dielectric layer and the plurality of control gate electrodes, the floating gate electrodes comprising a metal-semiconductor compound; and a charge blocking layer interposed between each of the plurality of control gate electrodes and each of the plurality of floating gate electrodes.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: July 5, 2016
    Assignee: SK Hynix Inc.
    Inventors: Sung-Jin Whang, Dong-Sun Sheen, Seung-Ho Pyi, Min-Soo Kim
  • Publication number: 20160181159
    Abstract: A method for fabricating a semiconductor device, including forming gate patterns over a substrate, forming conductive layer covering top and sidewalls of each gate pattern, forming a metal layer for a silicidation process over the conductive layer, and silicifying the conductive layer and the gate patterns using the metal layer.
    Type: Application
    Filed: February 29, 2016
    Publication date: June 23, 2016
    Inventors: Sung-Jin WHANG, Moon-Sig JOO, Yong-Seok EUN, Kwon HONG, Bo-Min SEO, Kyoung-Eun CHANG, Seung-Woo SHIN
  • Patent number: 9368219
    Abstract: A nonvolatile memory device includes a channel vertically extending from a substrate, a plurality of memory cells stacked along the channel; a source region connected to a first end portion of the channel, and a bit line connected to a second end portion of the channel, wherein the first end portion of the channel that adjoins the source region is formed as an undoped semiconductor layer or a semiconductor layer doped with P-type impurities.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: June 14, 2016
    Assignee: SK Hynix Inc.
    Inventors: Seiichi Aritome, Hyun-Seung Yoo, Sung-Jin Whang
  • Patent number: 9368645
    Abstract: This technology relates to a nonvolatile memory device and a method of fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode over a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each coupled with the pipe channel layer and extended in a direction substantially perpendicular to the substrate, a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers, and etch stop layers including metal silicide and formed over the pipe connection gate electrode.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: June 14, 2016
    Assignee: SK Hynix Inc.
    Inventors: Min-Soo Kim, Young-Jin Lee, Jin-Hae Choi, Joo-Hee Han, Sung-Jin Whang, Byung-Ho Lee
  • Patent number: 9362304
    Abstract: This technology relates to a nonvolatile memory device and a method of fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode configured to have a bottom buried in a groove formed in a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each coupled to the pipe channel layer and extended in a direction substantially perpendicular to the substrate, and a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers, wherein the pipe connection gate electrode includes a metal silicide layer formed within the groove. The electric resistance of the pipe connection gate electrode may be greatly reduced without an increase in a substantial height by forming the metal silicide layer buried in the substrate under the pipe connection gate electrode.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: June 7, 2016
    Assignee: SK Hynix Inc.
    Inventors: Min-Soo Kim, Young-Jin Lee, Jin-Hae Choi, Joo-Hee Han, Sung-Jin Whang, Byung-Ho Lee
  • Publication number: 20160155511
    Abstract: A nonvolatile memory device includes a channel vertically extending from a substrate, a plurality of memory cells stacked along the channel; a source region connected to a first end portion of the channel, and a bit line connected to a second end portion of the channel, wherein the first end portion of the channel that adjoins the source region is formed as an undoped semiconductor layer or a semiconductor layer doped with P-type impurities.
    Type: Application
    Filed: February 4, 2016
    Publication date: June 2, 2016
    Inventors: Seiichi ARITOME, Hyun-Seung YOO, Sung-Jin WHANG
  • Patent number: 9293337
    Abstract: A semiconductor device including a conductive layer, a diffusion barrier layer formed over the conductive layer, including a refractory metal compound, and acquired after a surface treatment, and a metal silicide layer formed over the diffusion barrier layer. The adhesion between a diffusion barrier layer and a metal silicide layer may be improved by increasing the surface energy of the diffusion barrier layer through a surface treatment. Therefore, although the metal silicide layer is fused in a high-temperature process, it is possible to prevent a void from being caused at the interface between the diffusion barrier layer and the metal silicide layer. Moreover, it is possible to increase the adhesion between a conductive layer and the diffusion barrier layer by increasing the surface energy of the conductive layer through the surface treatment.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: March 22, 2016
    Assignee: SK Hynix Inc.
    Inventors: Sung-Jin Whang, Moon-Sig Joo, Kwon Hong, Jung-Yeon Lim, Won-Kyu Kim, Bo-Min Seo, Kyoung-Eun Chang
  • Patent number: 9286988
    Abstract: A nonvolatile memory device includes a channel vertically extending from a substrate, a plurality of memory cells stacked along the channel; a source region connected to a first end portion of the channel, and a bit line connected to a second end portion of the channel, wherein the first end portion of the channel that adjoins the source region is formed as an undoped semiconductor layer or a semiconductor layer doped with P-type impurities.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: March 15, 2016
    Assignee: SK Hynix Inc.
    Inventors: Seiichi Aritome, Hyun-Seung Yoo, Sung-Jin Whang
  • Patent number: 9275904
    Abstract: A method for fabricating a semiconductor device, including forming gate patterns over a substrate, forming conductive layer covering top and sidewalls of each gate pattern, forming a metal layer for a silicidation process over the conductive layer, and silicifying the conductive layer and the gate patterns using the metal layer.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: March 1, 2016
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sung-Jin Whang, Moon-Sig Joo, Yong-Seok Eun, Kwon Hong, Bo-Min Seo, Kyoung-Eun Chang, Seung-Woo Shin
  • Publication number: 20150348990
    Abstract: This technology relates to a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode over a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each connected with the pipe channel layer and extended in a direction substantially perpendicular to the substrate, a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers, and metal silicide layers configured to be in contact with the pipe connection gate electrode. The electric resistance of the pipe connection gate electrode may be greatly reduced without deteriorating the characteristics of the memory layers by forming the metal silicide layers coming in contact with the pipe connection gate electrode.
    Type: Application
    Filed: August 7, 2015
    Publication date: December 3, 2015
    Inventors: Min-Soo KIM, Young-Jin LEE, Sung-Jin WHANG
  • Publication number: 20150311209
    Abstract: A three-dimensional (3-D) non-volatile memory device includes a plurality of word line structures extended in parallel and including a plurality of interlayer dielectric layers and a plurality of word lines that are alternately stacked over a substrate, a plurality of channels protruding from the substrate configured to penetrate the plurality of interlayer dielectric layers and the plurality of word lines, and an air gap formed between the plurality of word line structures.
    Type: Application
    Filed: July 9, 2015
    Publication date: October 29, 2015
    Inventors: Sung Jin WHANG, Ki Hong LEE
  • Patent number: 9159570
    Abstract: A non-volatile memory device includes a channel layer vertically extending from a substrate, a plurality of inter-layer dielectric layers and a plurality of gate electrodes that are alternately stacked along the channel layer, and an air gap interposed between the channel layer and each of the plurality of gate electrodes. The non-volatile memory device may improve erase operation characteristics by suppressing back tunneling of electrons by substituting a charge blocking layer interposed between a gate electrode and a charge storage layer with an air gap, and a method for fabricating the non-volatile memory device.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: October 13, 2015
    Assignee: SK Hynix Inc.
    Inventors: Min-Soo Kim, Dong-Sun Sheen, Seung-Ho Pyi, Sung-Jin Whang
  • Patent number: 9136394
    Abstract: This technology relates to a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode over a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each connected with the pipe channel layer and extended in a direction substantially perpendicular to the substrate, a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers, and metal silicide layers configured to be in contact with the pipe connection gate electrode. The electric resistance of the pipe connection gate electrode may be greatly reduced without deteriorating the characteristics of the memory layers by forming the metal silicide layers coming in contact with the pipe connection gate electrode.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: September 15, 2015
    Assignee: SK Hynix Inc.
    Inventors: Min-Soo Kim, Young-Jin Lee, Sung-Jin Whang
  • Patent number: 9130052
    Abstract: This technology relates to a nonvolatile memory device and a method of fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode over a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each coupled with the pipe channel layer and extended in a direction substantially perpendicular to the substrate, a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers, and etch stop layers including metal silicide and formed over the pipe connection gate electrode.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: September 8, 2015
    Assignee: SK Hynix Inc.
    Inventors: Min-Soo Kim, Young-Jin Lee, Jin-Hae Choi, Joo-Hee Han, Sung-Jin Whang, Byung-Ho Lee
  • Patent number: 9130053
    Abstract: This technology relates to a nonvolatile memory device and a method of fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode configured to have a bottom buried in a groove formed in a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each coupled to the pipe channel layer and extended in a direction substantially perpendicular to the substrate, and a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers, wherein the pipe connection gate electrode includes a metal silicide layer formed within the groove. The electric resistance of the pipe connection gate electrode may be greatly reduced without an increase in a substantial height by forming the metal silicide layer buried in the substrate under the pipe connection gate electrode.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: September 8, 2015
    Assignee: SK Hynix Inc.
    Inventors: Min-Soo Kim, Young-Jin Lee, Jin-Hae Choi, Joo-Hee Han, Sung-Jin Whang, Byung-Ho Lee
  • Publication number: 20150249095
    Abstract: This technology relates to a nonvolatile memory device and a method of fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode over a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each coupled with the pipe channel layer and extended in a direction substantially perpendicular to the substrate, a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers, and etch stop layers including metal silicide and formed over the pipe connection gate electrode.
    Type: Application
    Filed: May 13, 2015
    Publication date: September 3, 2015
    Inventors: Min-Soo KIM, Young-Jin LEE, Jin-Hae CHOI, Joo-Hee HAN, Sung-Jin WHANG, Byung-Ho LEE
  • Publication number: 20150236039
    Abstract: This technology relates to a nonvolatile memory device and a method of fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode configured to have a bottom buried in a groove formed in a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each coupled to the pipe channel layer and extended in a direction substantially perpendicular to the substrate, and a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers, wherein the pipe connection gate electrode includes a metal silicide layer formed within the groove. The electric resistance of the pipe connection gate electrode may be greatly reduced without an increase in a substantial height by forming the metal silicide layer buried in the substrate under the pipe connection gate electrode.
    Type: Application
    Filed: April 30, 2015
    Publication date: August 20, 2015
    Inventors: Min-Soo KIM, Young-Jin LEE, Jin-Hae CHOI, Joo-Hee HAN, Sung-Jin WHANG, Byung-Ho LEE