Abstract: Proposed is a system based on the Internet of Media Things (IoMT). The system may include at least one first sensor configured to perform a predetermined function in a target space or region, and a second sensor based on at least one of video or audio. The system may also include a first analysis processor configured to generate first analysis data of a set mission within the target space or region based on first data sensed by the first sensor. The system may further include a second analysis processor configured to generate second analysis data for a set mission within the target space or region based on second data sensed by the second sensor. The system may further include storage configured to store the sensed first data and second data and the first and second analysis data based on the identifier.

Abstract: A method of manufacturing a display device includes aligning light emitting elements in an emission area on a substrate, depositing an indium-tin alloy on an entire surface of the substrate at room temperature, heat-treating the indium-tin alloy to reflow along side surfaces of each of the light emitting elements, heat-treating the indium-tin alloy in an oxygen atmosphere to form indium tin oxide, and etching the indium tin oxide to form a first pixel electrode contacting first ends of at least a portion of the light emitting elements.

Abstract: A method of a terminal may comprise: receiving a first message including state information of a base station from the base station; identifying preliminary inactive state information included in the first message when the state information of the base station indicates a preliminary inactive state; and performing a cell selection based on the preliminary inactive state information.

Abstract: An organic light-emitting diode (“OLED”) includes a bottom electrode, a top electrode disposed opposite to the bottom electrode, and an organic layer that is interposed between the bottom electrode and the top electrode and includes a hole-transporting host and an electron-transporting host forming an exciplex and a phosphorescent dopant having a triplet energy which is lower than the triplet energy of the hole-transporting host, the triplet energy of the electron-transporting host, and the triplet energy of the exciplex, and a lighting device and a display apparatus including the OLED. Instead of a phosphorescent dopant, the fluorescent dopant having a singlet energy which is lower than the singlet energy of the exciplex may be also used.

Abstract: A super-steep switching device and an inverter device using the same are disclosed. The super-steep switching device includes a semiconductor channel disposed on a substrate and made of a semiconductor material having impact ionization characteristic; a source electrode and a drain electrode in contact with the semiconductor channel, wherein the source electrode and the drain electrode are disposed on the substrate and are spaced apart from each other; and a gate electrode disposed on the semiconductor channel so as to overlap only a portion of the semiconductor channel, wherein a top surface of the semiconductor channel includes a first area overlapping the gate electrode, and a second area non-overlapping the gate electrode, wherein a ratio of a length of the first area and a length of the second area is in a range of 1:0.1 to 0.4.

Abstract: A quantum dot including a core that includes a first semiconductor nanocrystal including zinc and selenium, and optionally sulfur and/or tellurium, and a shell that includes a second semiconductor nanocrystal including zinc, and at least one of sulfur or selenium is disclosed. The quantum dot has an average particle diameter of greater than or equal to about 13 nm, an emission peak wavelength in a range of about 440 nm to about 470 nm, and a full width at half maximum (FWHM) of an emission wavelength of less than about 25 nm. A method for preparing the quantum dot, a quantum dot-polymer composite including the quantum dot, and an electronic device including the quantum dot is also disclosed.

Abstract: A scrubber system may include a scrubber housing including a vertically extended cleaning space, an inflow chamber coupled to a bottom portion of the scrubber housing, and first and second inflow portions, each of which is configured to supply a gas into the inflow chamber. The inflow chamber may include a mixing space, and the mixing space may be connected to the cleaning space. The first inflow portion may include a first connection pipe coupled to the inflow chamber to provide a first connection path and the second inflow portion may include a second connection pipe coupled to the inflow chamber to provide a second connection path. The first and second connection paths may be extended toward the mixing space in opposite directions, respectively, and may be connected to opposite portions of the mixing space, respectively.

Abstract: The present disclosure provides an improvement to razor blade coating by a physical vapor deposition method, by forming a hard coating layer as a thin coating layer in which chromium boride, which is a nanocrystalline structure having high hardness, is dispersed in an amorphous mixture of chromium and boron, thereby improving the strength and hardness of the thin coating layer and securing the bonding force by chromium in the amorphous mixture between the hard coating layer and a blade substrate on which an edge of the razor blade is formed.

Abstract: Provided is a peptide composition for preventing or treating Alzheimer's dementia. A peptide or a salt substituent thereof according to the presently claimed subject matter exhibits effects such as suppression of LPS-mediated cytokine production, suppression of LPS-induced neuroinflammation, amelioration of cognitive impairment, suppression of beta amyloid or tau protein aggregation, and suppression of neuronal loss. The polypeptide or the salt substituent thereof can permeate the blood-brain barrier, and thus, is expected to be usefully used for preventing or treating Alzheimer's dementia.

Abstract: An orbit transition apparatus that transitions an orbit of a payload in outer space includes a rotating body, an adapter disposed on a center part of the rotating body for docking a payload, a launch module disposed outside of the rotating body for launching the payload, and a thruster for rotating the rotating body. The launch module may launch the payload to a target orbit.

Abstract: A memory device including: a loopback circuit for performing a loopback operation, wherein the loopback operation includes receiving, via a loopback channel, test signals provided from a test device and feeding back the test signals to the test device via the loopback channel; and an information management circuit for outputting information of the memory device to the loopback channel.

Abstract: A memory module includes semiconductor memory devices mounted on a circuit board and a control device mounted on the circuit board. The control device receives a command, an address, and a clock signal from an external device, and provides the command, the address, and the clock signal to the semiconductor memory devices. The control device, in a hidden training mode during a normal operation, performs a command/address training on at least one semiconductor memory device of the semiconductor memory devices by transmitting a first command/address and a first clock signal to the at least one semiconductor memory device and receiving a second command/address and a second clock signal in response to the first command/address and the first clock signal, from the at least one semiconductor memory device.

Abstract: A memory module includes semiconductor memory devices mounted on a circuit board and a control device mounted on the circuit board. The control device receives a command, an address, and a clock signal from an external device, and provides the command, the address, and the clock signal to the semiconductor memory devices. The control device, in a hidden training mode during a normal operation, performs a command/address training on at least one semiconductor memory device of the semiconductor memory devices by transmitting a first command/address and a first clock signal to the at least one semiconductor memory device and receiving a second command/address and a second clock signal in response to the first command/address and the first clock signal, from the at least one semiconductor memory device.

Abstract: A memory device including: a loopback circuit for performing a loopback operation, wherein the loopback operation comprises receiving, via a loopback channel, test signals provided from a test device and feeding back the test signals to the test device via the loopback channel; and an information management circuit for outputting information of the memory device to the loopback channel.

Abstract: A data receiver includes a first buffer circuit and a second buffer circuit. The first buffer circuit varies a resistance of a data path and a resistance of a reference voltage path based on a plurality of control signals, and adjusts a voltage level of an input data signal and a level of a reference voltage to generate an internal data signal and an internal reference voltage based on the varied resistance of the data path and the varied resistance of the reference voltage path. The second buffer circuit compares the internal data signal with the internal reference voltage to generate a data signal.

Abstract: A structure of an integrated circuit module includes a wiring board, a plurality of integrated circuits and at least one terminating resistance circuit. The wiring board has a mounting region on at least one surface thereof. The plurality of integrated circuits are mounted in the mounting region of the wiring board and spaced from one another in a first direction. The at least one terminating resistance circuit is arranged between at least two adjacent integrated circuits, and coupled to an output of a last of the plurality of integrated circuits.

Abstract: A memory system includes; a main board having memory bus with a wiring line communicating a signal from a memory controller mounted on the main board, first and second module sockets mounted on the main board and connecting the wiring line to first and second memory modules respectively inserted into the first and second module sockets, where the first memory module includes a first electrode connected to the wiring line and the second memory module includes a second electrode connected to the wiring line, and first and second stub resistors disposed on the main board and arranged as primary dual-branching stub resistors forming a T-branch connection structure between the first and second electrodes and a branching node connected to the wiring line.

Abstract: A data receiver includes a first buffer circuit and a second buffer circuit. The first buffer circuit varies a resistance of a data path and a resistance of a reference voltage path based on a plurality of control signals, and adjusts a voltage level of an input data signal and a level of a reference voltage to generate an internal data signal and an internal reference voltage based on the varied resistance of the data path and the varied resistance of the reference voltage path. The second buffer circuit compares the internal data signal with the internal reference voltage to generate a data signal.

Abstract: The invention provides a thermal-emitting memory module, a thermal-emitting module socket, and a computer system comprising the thermal-emitting memory module and the thermal-emitting module socket. An embodiment of the thermal-emitting module includes: a module substrate having electrically-conductive traces; and a semiconductor device disposed on the module substrate and coupled to the electrically-conductive traces, the module substrate including a thermal-emitting portion disposed in proximity of the semiconductor device without directly contacting the semiconductor device.

Abstract: A memory module includes a plurality of buses and a plurality of memory chips arranged close to each other along each of the plurality of buses. An N-th memory chip, where N is an integer, of the plurality of memory chips is connected to any one of the plurality of buses, and each of the other memory chips of the plurality of memory chips, except for the N-th memory chip, is connected to the other one of the plurality of buses.