Abstract: A semiconductor device includes a first active pattern extending lengthwise along a first direction and a second active pattern extending lengthwise along the first direction and spaced apart from the first active pattern in the first direction. The device also includes a field insulating film between the first active pattern and the second active pattern. An upper surface of the field insulating film is lower than or coplanar with upper surfaces of the first and second active patterns. The device further includes an element isolation structure in an isolation trench in the first active pattern and the field insulating film. An upper surface of the element isolation structure is higher than the upper surfaces of the first and second active patterns.

Abstract: Provided is a method and apparatus for processing instructions using a processing-in-memory (PIM). A PIM management apparatus includes: a PIM directory comprising a reader-writer lock regarding a memory address that an instruction accesses; and a locality tracer configured to figure out locality regarding the memory address that the instruction accesses and determine whether or not an object that executes the instruction is a PIM.

Abstract: A semiconductor device includes a first active pattern extending lengthwise along a first direction and a second active pattern extending lengthwise along the first direction and spaced apart from the first active pattern in the first direction. The device also includes a field insulating film between the first active pattern and the second active pattern. An upper surface of the field insulating film is lower than or coplanar with upper surfaces of the first and second active patterns. The device further includes an element isolation structure in an isolation trench in the first active pattern and the field insulating film. An upper surface of the element isolation structure is higher than the upper surfaces of the first and second active patterns.

Abstract: A method of visualizing an image, a device and a system using the same. The method of visualizing, by a device operatively connected with an image provision server, an image configured in a hierarchical structure including a plurality of levels includes receiving tile visualization information in an encoded form from the image provision server, the tile visualization information including a tile visualization type determined according to whether at least one tile belonging to each of the levels of the image includes data; decoding the encoded tile visualization information and obtaining the tile visualization information; making a request to the image providing server for data for a target level and tile, which are to be visualized according to the tile visualization information; and displaying an image, which is to be visualized, received from the image provision server.

Abstract: A method for fabricating semiconductor device includes forming an alternating stack that includes a lower multi-layered stack and an upper multi-layered stack by alternately stacking a dielectric layer and a sacrificial layer over a substrate, forming a vertical trench that divides the upper multi-layered stack into dummy stacks, and forming an asymmetric stepped trench that is extended downward from the vertical trench to divide the lower multi-layered stack into a pad stack and a dummy pad stack, wherein forming the asymmetric stepped trench includes forming a first stepped sidewall that is defined at an edge of the pad stack, and forming a second stepped sidewall that is defined at an edge of the dummy pad stack and occupies less area than the first stepped sidewall.

Abstract: A FINFET includes a first fin extending in a first direction on a substrate and, a second fin extending in the first direction and spaced apart from the first fin in the first direction. A third fin is provided with a long side shorter than long sides of the first fin and the second fin and is disposed between the first fin and the second fin. A first gate structure extends in a second direction different from the first direction and crosses the first fin. A device isolation layer is disposed on a lower sidewall of each of the first, second and third fins and is formed to extend in the first direction. An electrically insulating diffusion break region includes a first portion crossing between the first fin and the third fin, a second portion crossing between the second fin and the third fin, and a third portion disposed between the first portion and the second portion on the third fin. The diffusion break region extends in the second direction on the device isolation layer.

Abstract: Proposed are a method and apparatus for accelerating data processing in a neural network. The apparatus for accelerating data processing in a neural network may include: a control unit configured to quantize data by at least one method according to a characteristic of data calculated at a node forming at least one layer constituting the neural network, and to separately perform calculation at the node according to the quantized data; and memory configured to store the quantized data.

Abstract: A semiconductor device and a method for fabricating the same, the device including an active pattern extending in a first direction on a substrate; a field insulating film surrounding a part of the active pattern; a first gate structure extending in a second direction on the active pattern and the field insulating film, a second gate structure spaced apart from the first gate structure and extending in the second direction on the active pattern and the field insulating film; and a first device isolation film between the first and second gate structure, wherein a side wall of the first gate structure facing the first device isolation film includes an inclined surface having an acute angle with respect to an upper surface of the active pattern, and a lowermost surface of the first device isolation film is lower than or substantially coplanar with an uppermost surface of the field insulating film.

Abstract: A semiconductor device includes a first active pattern extending lengthwise along a first direction and a second active pattern extending lengthwise along the first direction and spaced apart from the first active pattern in the first direction. The device also includes a field insulating film between the first active pattern and the second active pattern. An upper surface of the field insulating film is lower than or coplanar with upper surfaces of the first and second active patterns. The device further includes an element isolation structure in an isolation trench in the first active pattern and the field insulating film. An upper surface of the element isolation structure is higher than the upper surfaces of the first and second active patterns.

Abstract: A FINFET includes a first fin extending in a first direction on a substrate and, a second fin extending in the first direction and spaced apart from the first fin in the first direction. A third fin is provided with a long side shorter than long sides of the first fin and the second fin and is disposed between the first fin and the second fin. A first gate structure extends in a second direction different from the first direction and crosses the first fin. A device isolation layer is disposed on a lower sidewall of each of the first, second and third fins and is formed to extend in the first direction. An electrically insulating diffusion break region includes a first portion crossing between the first fin and the third fin, a second portion crossing between the second fin and the third fin, and a third portion disposed between the first portion and the second portion on the third fin. The diffusion break region extends in the second direction on the device isolation layer.

Abstract: A circuit for selecting a row of memory cells of a memory device to be refreshed may include: a cold table suitable for storing as a cold row a row selected as a hammered row when the row selected as the hammered row is neither one of cold rows stored in the cold table nor one of hot rows stored in a hot table; and the hot table suitable for storing, as a hot row, the row selected as the hammered row when the row selected as the hammered row is one of the cold rows stored in the cold table.

Abstract: A method of visualizing an image, a device and a system using the same. The method of visualizing, by a device operatively connected with an image provision server, an image configured in a hierarchical structure including a plurality of levels includes receiving tile visualization information in an encoded form from the image provision server, the tile visualization information including a tile visualization type determined according to whether at least one tile belonging to each of the levels of the image includes data; decoding the encoded tile visualization information and obtaining the tile visualization information; making a request to the image providing server for data for a target level and tile, which are to be visualized according to the tile visualization information; and displaying an image, which is to be visualized, received from the image provision server.

Abstract: A method and a mobile terminal for controlling the icons of the mobile terminal are provided. The method includes displaying at least one icon on a widget screen corresponding with a function for changing the size of the icon displayed on a touch screen; receiving a selection of an icon to which the function is to be applied; activating an attribute of the selected icon; and adjusting, if a side of the selected icon is dragged on the widget screen, a size of the selected icon according to a direction of the drag.

Abstract: A circuit for selecting a row of memory cells of a memory device to be refreshed may include: a cold table suitable for storing as a cold row a row selected as a hammered row when the row selected as the hammered row is neither one of cold rows stored in the cold table nor one of hot rows stored in a hot table; and the hot table suitable for storing, as a hot row, the row selected as the hammered row when the row selected as the hammered row is one of the cold rows stored in the cold table.

Abstract: Provided is a method and apparatus for processing instructions using a processing-in-memory (PIM). A PIM management apparatus includes: a PIM directory comprising a reader-writer lock regarding a memory address that an instruction accesses; and a locality tracer configured to figure out locality regarding the memory address that the instruction accesses and determine whether or not an object that executes the instruction is a PIM.

Abstract: A power reduction method for a multi-path receiver including multi-receivers, includes detecting a state of the multi-receivers, and controlling clock gating or power gating of the multi-receivers based on the state.

Abstract: Provided is a reconfigurable processor that may process a first type of operation in first mode using a first group of functional units, and process a second type of operation in second mode using a second group of functional units. The reconfigurable processor may selectively supply power to either the first group or the second group, in response to a mode-switch signal or a mode-switch instruction.

Abstract: An apparatus and method for controlling a low-voltage memory in a mobile communication system are provided. The apparatus includes a memory for storing data including at least one error caused by a low-voltage, and an error correction unit for identifying whether the at least one error exists in the memory according to a first bit set in a local buffer of an error correction code storage, for comparing location information on the error data read from the memory and location information on error data of at least one protection set in the local buffer of the error correction code storage when it is determined that the at least one error exists in the memory, for generating an error correction code as a result of the comparison, and for correcting the error data of the memory according to the error correction code.

Abstract: A method of operating a memory system includes the operations of outputting dirty cache lines from a data cache to a volatile memory device as instructions are executed, and outputting from the volatile memory device to a non-volatile memory device as many dirty cache lines as the size of a page of the non-volatile memory.

Abstract: An apparatus and method for controlling a low-voltage memory in a mobile communication system are provided. The apparatus includes a memory for storing data including at least one error caused by a low-voltage, and an error correction unit for identifying whether the at least one error exists in the memory according to a first bit set in a local buffer of an error correction code storage, for comparing location information on the error data read from the memory and location information on error data of at least one protection set in the local buffer of the error correction code storage when it is determined that the at least one error exists in the memory, for generating an error correction code as a result of the comparison, and for correcting the error data of the memory according to the error correction code.