Patents by Inventor Sung-kee Han
Sung-kee Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10651179Abstract: A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.Type: GrantFiled: May 30, 2018Date of Patent: May 12, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hong-bae Park, Ja-hum Ku, Myeong-cheol Kim, Jin-wook Lee, Sung-kee Han
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Patent number: 10312340Abstract: A semiconductor device includes a first transistor comprising a first dielectric film on a substrate and a first work function metal film of a first conductivity type on the first dielectric film, a second transistor comprising a second dielectric film on the substrate and a second work function metal film of the first conductivity type on the second dielectric film, and a third transistor comprising a third dielectric film on the substrate and a third work function metal film of the first conductivity type on the third dielectric film. The first dielectric film comprises a work function tuning material and the second dielectric film does not comprise the work function tuning material. The first work function metal film has different thickness than the third work function metal film. Related methods are also described.Type: GrantFiled: September 27, 2017Date of Patent: June 4, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Wan-Don Kim, Oh-Seong Kwon, Hoon-Joo Na, Hyeok-Jun Son, Jae-Yeol Song, Sung-Kee Han, Sang-Jin Hyun
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Publication number: 20180277547Abstract: A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.Type: ApplicationFiled: May 30, 2018Publication date: September 27, 2018Inventors: Hong-bae PARK, Ja-hum KU, Myeong-cheol KIM, Jin-wook LEE, Sung-kee HAN
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Patent number: 10014304Abstract: A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.Type: GrantFiled: October 25, 2016Date of Patent: July 3, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hong-bae Park, Ja-hum Ku, Myeong-cheol Kim, Jin-wook Lee, Sung-kee Han
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Publication number: 20180019314Abstract: A semiconductor device includes a first transistor comprising a first dielectric film on a substrate and a first work function metal film of a first conductivity type on the first dielectric film, a second transistor comprising a second dielectric film on the substrate and a second work function metal film of the first conductivity type on the second dielectric film, and a third transistor comprising a third dielectric film on the substrate and a third work function metal film of the first conductivity type on the third dielectric film. The first dielectric film comprises a work function tuning material and the second dielectric film does not comprise the work function tuning material. The first work function metal film has different thickness than the third work function metal film. Related methods are also described.Type: ApplicationFiled: September 27, 2017Publication date: January 18, 2018Inventors: Wan-Don Kim, Oh-Seong KWON, Hoon-Joo NA, Hyeok-Jun SON, Jae-Yeol SONG, Sung-Kee HAN, Sang-Jin HYUN
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Patent number: 9780183Abstract: A semiconductor device includes a first transistor comprising a first dielectric film on a substrate and a first work function metal film of a first conductivity type on the first dielectric film, a second transistor comprising a second dielectric film on the substrate and a second work function metal film of the first conductivity type on the second dielectric film, and a third transistor comprising a third dielectric film on the substrate and a third work function metal film of the first conductivity type on the third dielectric film. The first dielectric film comprises a work function tuning material and the second dielectric film does not comprise the work function tuning material. The first work function metal film has different thickness than the third work function metal film. Related methods are also described.Type: GrantFiled: January 6, 2016Date of Patent: October 3, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Wan-Don Kim, Oh-Seong Kwon, Hoon-Joo Na, Hyeok-Jun Son, Jae-Yeol Song, Sung-Kee Han, Sang-Jin Hyun
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Publication number: 20170040328Abstract: A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.Type: ApplicationFiled: October 25, 2016Publication date: February 9, 2017Inventors: Hong-bae PARK, Ja-hum KU, Myeong-cheol KIM, Jin-wook LEE, Sung-kee HAN
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Patent number: 9508727Abstract: A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.Type: GrantFiled: September 14, 2015Date of Patent: November 29, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hong-bae Park, Ja-hum Ku, Myeong-cheol Kim, Jin-wook Lee, Sung-kee Han
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Publication number: 20160225868Abstract: A semiconductor device includes a first transistor comprising a first dielectric film on a substrate and a first work function metal film of a first conductivity type on the first dielectric film, a second transistor comprising a second dielectric film on the substrate and a second work function metal film of the first conductivity type on the second dielectric film, and a third transistor comprising a third dielectric film on the substrate and a third work function metal film of the first conductivity type on the third dielectric film. The first dielectric film comprises a work function tuning material and the second dielectric film does not comprise the work function tuning material. The first work function metal film has different thickness than the third work function metal film. Related methods are also described.Type: ApplicationFiled: January 6, 2016Publication date: August 4, 2016Inventors: Wan-Don KIM, Oh-Seong KWON, Hoon-Joo NA, Hyeok-Jun SON, Jae-Yeol SONG, Sung-Kee HAN, Sang-Jin HYUN
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Publication number: 20160133632Abstract: A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.Type: ApplicationFiled: September 14, 2015Publication date: May 12, 2016Inventors: Hong-bae PARK, Ja-hum KU, Myeong-cheol KIM, Jin-wook LEE, Sung-kee HAN
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Patent number: 9337057Abstract: Provided are methods for fabricating semiconductor devices. The methods for fabricating the semiconductor devices may include forming a first interlayer insulation film including a trench on a substrate, forming a high-k layer along an inner sidewall and a bottom surface of the trench, forming a first work function control film including impurities along the high-k layer, removing the impurities from the first work function control film to reduce surface resistance of the first work function control film by about 30% to about 60% and forming a gate metal in the trench.Type: GrantFiled: July 17, 2015Date of Patent: May 10, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Moon-Kyu Park, Oh-Seong Kwon, Sung-Kee Han, Sang-Jin Hyun
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Publication number: 20160020118Abstract: Provided are methods for fabricating semiconductor devices. The methods for fabricating the semiconductor devices may include forming a first interlayer insulation film including a trench on a substrate, forming a high-k layer along an inner sidewall and a bottom surface of the trench, forming a first work function control film including impurities along the high-k layer, removing the impurities from the first work function control film to reduce surface resistance of the first work function control film by about 30% to about 60% and forming a gate metal in the trench.Type: ApplicationFiled: July 17, 2015Publication date: January 21, 2016Inventors: Moon-Kyu PARK, Oh-Seong KWON, Sung-Kee HAN, Sang-Jin HYUN
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Patent number: 9059090Abstract: A method of fabricating a semiconductor device includes forming a first gate pattern and a dummy gate pattern on a first active area and a second active area of a substrate, respectively, the first gate pattern including a first gate insulating layer and a silicon gate electrode, removing the dummy gate pattern to expose a surface of the substrate in the second active area, forming a second gate pattern including a second gate insulating layer and a metal gate electrode on the exposed surface of the substrate, the first gate insulating layer having a thickness larger than a thickness of the second gate insulating layer, and forming a gate silicide on the silicon gate electrode after forming the second gate pattern.Type: GrantFiled: April 21, 2014Date of Patent: June 16, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ju-Youn Kim, Hyun-Min Choi, Sung-Kee Han, Je-Don Kim
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Patent number: 9048307Abstract: A semiconductor device having reduced leakage current and increased capacitance without increasing an equivalent oxide thickness (EOT) can be manufactured by a method that includes providing a substrate having a dummy gate pattern; forming a gate forming trench by removing the dummy gate pattern; forming a stacked insulation layer within the gate forming trench, wherein the forming of the stacked insulation layer includes forming a first high-k dielectric layer, forming a second high-k dielectric layer by performing heat treatment on the first high-k dielectric layer, and, after the heat treatment, forming a third high-k dielectric layer on the second high-k dielectric layer, the third high-k dielectric layer having a higher relative permittivity than the second high-k dielectric layer and having a dielectric constant of 40 or higher; and forming a gate electrode within the gate forming trench.Type: GrantFiled: June 14, 2012Date of Patent: June 2, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Yeol Song, Jeong-Hee Han, Sang-Jin Hyun, Hyeok-Jun Son, Sung-Kee Han
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Publication number: 20140227868Abstract: A method of fabricating a semiconductor device includes forming a first gate pattern and a dummy gate pattern on a first active area and a second active area of a substrate, respectively, the first gate pattern including a first gate insulating layer and a silicon gate electrode, removing the dummy gate pattern to expose a surface of the substrate in the second active area, forming a second gate pattern including a second gate insulating layer and a metal gate electrode on the exposed surface of the substrate, the first gate insulating layer having a thickness larger than a thickness of the second gate insulating layer, and forming a gate silicide on the silicon gate electrode after forming the second gate pattern.Type: ApplicationFiled: April 21, 2014Publication date: August 14, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: JU-YOUN KIM, HYUN-MIN CHOI, SUNG-KEE HAN, JE-DON KIM
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Patent number: 8772146Abstract: A method of fabricating a semiconductor device includes forming a first gate pattern and a dummy gate pattern on a first active area and a second active area of a substrate, respectively, the first gate pattern including a first gate insulating layer and a silicon gate electrode, removing the dummy gate pattern to expose a surface of the substrate in the second active area, forming a second gate pattern including a second gate insulating layer and a metal gate electrode on the exposed surface of the substrate, the first gate insulating layer having a thickness larger than a thickness of the second gate insulating layer, and forming a gate silicide on the silicon gate electrode after forming the second gate pattern.Type: GrantFiled: August 28, 2012Date of Patent: July 8, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Ju-Youn Kim, Hyun-Min Choi, Sung-Kee Han, Je-Don Kim
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Publication number: 20140065809Abstract: A method of fabricating a semiconductor device includes forming a first gate pattern and a dummy gate pattern on a first active area and a second active area of a substrate, respectively, the first gate pattern including a first gate insulating layer and a silicon gate electrode, removing the dummy gate pattern to expose a surface of the substrate in the second active area, forming a second gate pattern including a second gate insulating layer and a metal gate electrode on the exposed surface of the substrate, the first gate insulating layer having a thickness larger than a thickness of the second gate insulating layer, and forming a gate silicide on the silicon gate electrode after forming the second gate pattern.Type: ApplicationFiled: August 28, 2012Publication date: March 6, 2014Inventors: Ju-Youn Kim, Hyun-Min Choi, Sung-Kee Han, Je-Don Kim
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Publication number: 20120319216Abstract: A semiconductor device having reduced leakage current and increased capacitance without increasing an equivalent oxide thickness (EOT) can be manufactured by a method that includes providing a substrate having a dummy gate pattern; forming a gate forming trench by removing the dummy gate pattern; forming a stacked insulation layer within the gate forming trench, wherein the forming of the stacked insulation layer includes forming a first high-k dielectric layer, forming a second high-k dielectric layer by performing heat treatment on the first high-k dielectric layer, and, after the heat treatment, forming a third high-k dielectric layer on the second high-k dielectric layer, the third high-k dielectric layer having a higher relative permittivity than the second high-k dielectric layer and having a dielectric constant of 40 or higher; and forming a gate electrode within the gate forming trench.Type: ApplicationFiled: June 14, 2012Publication date: December 20, 2012Inventors: Jae-Yeol Song, Jeong-Hee Han, Sang-Jin Hyun, Hyeok-Jun Son, Sung-Kee Han
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Publication number: 20110193181Abstract: A semiconductor includes a channel region in a semiconductor substrate, a gate dielectric film on the channel region, and a gate on the gate dielectric film. The gate includes a doped metal nitride film, formed from a nitride of a first metal and doped with a second metal which is different from the first metal, and a conductive polysilicon layer formed on the doped metal nitride film. The gate may further include a metal containing capping layer interposed between the doped metal nitride film and the conductive polysilicon layer.Type: ApplicationFiled: April 19, 2011Publication date: August 11, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyung-suk JUNG, Jong-ho LEE, Sung-kee HAN, Ha-jin LIM
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Patent number: 7952118Abstract: A semiconductor includes a channel region in a semiconductor substrate, a gate dielectric film on the channel region, and a gate on the gate dielectric film. The gate includes a doped metal nitride film, formed from a nitride of a first metal and doped with a second metal which is different from the first metal, and a conductive polysilicon layer formed on the doped metal nitride film. The gate may further include a metal containing capping layer interposed between the doped metal nitride film and the conductive polysilicon layer.Type: GrantFiled: November 28, 2007Date of Patent: May 31, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Hyung-suk Jung, Jong-ho Lee, Sung-kee Han, Ha-jin Lim