Patents by Inventor Sung-Lae Cho

Sung-Lae Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10410990
    Abstract: A jig for bonding a semiconductor chip may include a pressurizing portion and at least one opening. The pressuring portion may be configured to pressurize an upper surface of the semiconductor chip bonded to a package substrate via a bump and a flux using a laser. The opening may be surrounded by the pressurizing portion. The laser irradiated to the bump and the flux may be transmitted through the opening. A vapor generated from the flux by the laser may be discharged through the opening. Thus, the contamination of the jig caused by the vapor may be prevented so that a transmissivity of the laser through the jig may be maintained.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: September 10, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Man-Hee Han, Dae-Sang Chan, Sung-Il Cho, Jung-Lae Jung
  • Publication number: 20180250905
    Abstract: The present invention relates to a mini hot press apparatus, and more particularly, to an apparatus which can be used for making or annealing a polycrystalline material by pressurization and heating in various surrounding environments such as in a low vacuum, high vacuum, ultrahigh vacuum, high pressure gas, gas flow, even in air, etc.
    Type: Application
    Filed: September 9, 2016
    Publication date: September 6, 2018
    Inventors: Sung-Lae CHO, Hae Woong KWON, Van Quang NGUYEN, Eun Ji PARK, Eun Jung PARK, Mal Sik KIM
  • Publication number: 20170084834
    Abstract: A variable resistance material layer including germanium (Ge), antimony (Sb), tellurium (Te), and at least one type of impurities X. The variable resistance material layer having a composition represented by a chemical formula of Xp(GeaSb(1-a-b)Teb)(1-p), wherein an atomic concentration of the impurities X is in a range of 0<p?0.2, an atomic concentration of Ge is in a range of 0.05?a<0.19, and an atomic concentration of Te is in a range of 0.42?b?0.56.
    Type: Application
    Filed: December 1, 2016
    Publication date: March 23, 2017
    Inventors: Do-Hyung Kim, Jong-Uk Kim, Dong-Ho Ahn, Sung-Lae Cho
  • Patent number: 9543513
    Abstract: A variable resistance material layer including germanium (Ge), antimony (Sb), tellurium (Te), and at least one type of impurities X. The variable resistance material layer having a composition represented by a chemical formula of Xp(GeaSb(1-a-b)Teb)(1-p), wherein an atomic concentration of the impurities X is in a range of 0<p?0.2, an atomic concentration of Ge is in a range of 0.05?a<0.19, and an atomic concentration of Te is in a range of 0.42?b?0.56.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: January 10, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Do-Hyung Kim, Jong-Uk Kim, Dong-Ho Ahn, Sung-Lae Cho
  • Publication number: 20160181521
    Abstract: A variable resistance material layer including germanium (Ge), antimony (Sb), tellurium (Te), and at least one type of impurities X. The variable resistance material layer having a composition represented by a chemical formula of Xp(GeaSb(1-a-b)Teb)(1-p), wherein an atomic concentration of the impurities X is in a range of 0<p?0.2, an atomic concentration of Ge is in a range of 0.05?a<0.19, and an atomic concentration of Te is in a range of 0.42?b?0.56.
    Type: Application
    Filed: December 10, 2015
    Publication date: June 23, 2016
    Inventors: Do-Hyung Kim, Jong-Uk KIM, Dong-Ho AHN, Sung-Lae CHO
  • Patent number: 9318700
    Abstract: In a method of manufacturing a phase change memory device, an insulating interlayer having a through opening is formed on a substrate, at least one conformal phase change material layer pattern is formed along the sides of the opening, and a plug-like phase change material pattern having a composition different from that of each conformal phase change material layer pattern is formed on the at least one conformal phase change material layer pattern as occupying a remaining portion of the opening. Energy is applied to the phase change material layer patterns to form a mixed phase change material layer pattern including elements from the conformal and plug-like phase change material layer patterns.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: April 19, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Zhe Wu, Jeong-Hee Park, Dong-Ho Ahn, Jung-Hwan Park, Jun-Ku Ahn, Sung-Lae Cho, Hideki Horii
  • Publication number: 20150364678
    Abstract: In a method of manufacturing a phase change memory device, an insulating interlayer having a through opening is formed on a substrate, at least one conformal phase change material layer pattern is formed along the sides of the opening, and a plug-like phase change material pattern having a composition different from that of each conformal phase change material layer pattern is formed on the at least one conformal phase change material layer pattern as occupying a remaining portion of the opening. Energy is applied to the phase change material layer patterns to form a mixed phase change material layer pattern including elements from the conformal and plug-like phase change material layer patterns.
    Type: Application
    Filed: June 16, 2015
    Publication date: December 17, 2015
    Inventors: ZHE WU, JEONG-HEE PARK, DONG-HO AHN, JUNG-HWAN PARK, JUN-KU AHN, SUNG-LAE CHO, HIDEKI HORII
  • Patent number: 8993441
    Abstract: A method of forming a thin layer and a method of manufacturing a phase change memory device, the method of forming a thin layer including providing a first deposition source onto a substrate, the first deposition source not including tellurium; and providing a second deposition source onto the substrate, the second deposition source including a first tellurium precursor represented by the following Formula 1 and a second tellurium precursor represented by following the Formula 2: Te(CH(CH3)2)2??Formula 1 Ten(CH(CH3)2)2??Formula 2 wherein, in Formula 2, n is an integer greater than or equal to 2.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: March 31, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Do-Hyung Kim, Eun-Tae Kim, Sung-Lae Cho
  • Patent number: 8852686
    Abstract: In one aspect, a method of forming a phase change material layer is provided. The method includes supplying a reaction gas including the composition of Formula 1 into a reaction chamber, supplying a first source which includes Ge(II) into the reaction chamber, and supplying a second source into the reaction chamber. Formula 1 is NR1R2R3, where R1, R2 and R3 are each independently at least one selected from the group consisting of H, CH3, C2H5, C3H7, C4H9, Si(CH3)3, NH2, NH(CH3), N(CH3)2, NH(C2H5) and N(C2H5)2.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: October 7, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byoung-jae Bae, Sung-lae Cho, Jin-il Lee, Hye-young Park, Do-hyung Kim
  • Publication number: 20140273395
    Abstract: A method of forming a thin layer and a method of manufacturing a phase change memory device, the method of forming a thin layer including providing a first deposition source onto a substrate, the first deposition source not including tellurium; and providing a second deposition source onto the substrate, the second deposition source including a first tellurium precursor represented by the following Formula 1 and a second tellurium precursor represented by following the Formula 2: Te(CH(CH3)2)2??Formula 1 Ten(CH(CH3)2)2??Formula 2 wherein, in Formula 2, n is an integer greater than or equal to 2.
    Type: Application
    Filed: February 25, 2014
    Publication date: September 18, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Do-Hyung KIM, Eun-Tae KIM, Sung-Lae CHO
  • Patent number: 8834968
    Abstract: In one aspect, a method of forming a phase change material layer is provided. The method includes supplying a reaction gas including the composition of Formula 1 into a reaction chamber, supplying a first source which includes Ge(II) into the reaction chamber, and supplying a second source into the reaction chamber. Formula 1 is NR1R2R3, where R1, R2 and R3 are each independently at least one selected from the group consisting of H, CH3, C2H5, C3H7, C4H9, Si(CH3)3, NH2, NH(CH3), N(CH3)2, NH(C2H5) and N(C2H5)2.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: September 16, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byoung-Jae Bae, Sung-Lae Cho, Jin-Il Lee, Hye-Young Park, Do-Hyung Kim
  • Patent number: 8790976
    Abstract: A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: July 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gyu-Hwan Oh, Sung-Lae Cho, Byoung-Jae Bae, Ik-Soo Kim, Dong-Hyun Im, Doo-Hwan Park, Kyoung-Ha Eom, Sung-Un Kwon, Chul-Ho Shin, Sang-Sup Jeong
  • Patent number: 8703237
    Abstract: Provided are methods of forming a material layer by chemically adsorbing metal atoms to a substrate having anions formed on the surface thereof, and a method of fabricating a memory device by using the material layer forming method. Accordingly, a via hole with a small diameter can be filled with a material layer without forming voids or seams. Thus, a reliable memory device can be obtained.
    Type: Grant
    Filed: May 14, 2009
    Date of Patent: April 22, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hye-young Park, Sung-lae Cho, Jin-il Lee, Do-hyung Kim, Dong-hyun Im
  • Patent number: 8644062
    Abstract: A multi-level memory device includes an insulating layer having an opening therein, and a multi-level cell (MLC) formed in the opening that has a resistance level varies based on the data stored therein. The MLC is configured to have a resistance level that varies as write pulses having the same pulse height and different pulse widths are applied to the MLC.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: February 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ik-Soo Kim, Sung-Lae Cho, Do-Hyung Kim, Hyeong-Geun An, Dong-Hyun Im, Eun-Hee Cho
  • Patent number: 8625325
    Abstract: A non-volatile memory device includes a plurality of word lines, a plurality of bit lines, and an array of variable resistance memory cells each electrically connected between a respective word line and a respective bit line. Each of the memory cells includes first and second resistance variable patterns electrically connected in series between first and second electrodes. A material composition of the first resistance variable pattern is different than a material composition of the second resistance variable pattern. Multi-bit data states of each memory cell are defined by a contiguous increase in size of a programmable high-resistance volume within the first and second resistance variable patterns.
    Type: Grant
    Filed: August 10, 2010
    Date of Patent: January 7, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeong-Geun An, Ik-Soo Kim, Hee-Ju Shin, Dong-Hyun Im, Sung-Lae Cho, Eun-Hee Cho
  • Publication number: 20130302966
    Abstract: A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.
    Type: Application
    Filed: July 15, 2013
    Publication date: November 14, 2013
    Inventors: Gyu-Hwan Oh, Sung-Lae Cho, Byoung-Jae Bae, Ik-Soo Kim, Dong-Hyun Im, Doo-Hwan Park, Kyoung-Ha Eom, Sung-Un Kwon, Chul-Ho Shin, Sang-Sup Jeong
  • Patent number: 8580606
    Abstract: A method of forming a resistance variable memory device, the method including forming a diode on a semiconductor substrate; forming a lower electrode on the diode; forming a first insulating film on the lower electrode, the first insulating film having an opening; forming a resistance variable film filling the opening such that the resistance variable film includes an amorphous region adjacent to a sidewall of the opening and a crystalline region adjacent to the lower electrode; and forming an upper electrode on the resistance variable film.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: November 12, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong-Hee Park, Jung-Hwan Park, Hideki Horii, Sung-Lae Cho
  • Patent number: 8507353
    Abstract: A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: August 13, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gyu-Hwan Oh, Sung-Lae Cho, Byoung-Jae Bae, Ik-Soo Kim, Dong-Hyun Im, Doo-Hwan Park, Kyoung-Ha Eom, Sung-Un Kwon, Chul-Ho Shin, Sang-Sup Jeong
  • Patent number: 8502184
    Abstract: A nonvolatile memory device and a method of fabricating the same are provided. The nonvolatile memory device includes a conductive pillar that extends from a substrate in a first direction, a variable resistor that surrounds the conductive pillar, a switching material layer that surrounds the variable resistor, a first conductive layer that extends in a second direction, and a first electrode that extends in a third direction and contacts the first conductive layer and the switching material layer. Not one of the first, second, and third directions is parallel to another one of the first, second, and third directions.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: August 6, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeong-Geun An, Sung-Lae Cho, Ik-Soo Kim, Dong-Hyun Im, Eun-Hee Cho
  • Publication number: 20130101491
    Abstract: In one aspect, a method of forming a phase change material layer is provided. The method includes supplying a reaction gas including the composition of Formula 1 into a reaction chamber, supplying a first source which includes Ge(II) into the reaction chamber, and supplying a second source into the reaction chamber. Formula 1 is NR1R2R3, where R1, R2 and R3 are each independently at least one selected from the group consisting of H, CH3, C2H5, C3H7, C4H9, Si(CH3)3, NH2, NH(CH3), N(CH3)2, NH(C2H5) and N(C2H5)2.
    Type: Application
    Filed: December 7, 2012
    Publication date: April 25, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byoung-Jae Bae, Sung-Lae Cho, Jin-Il Lee, Hye-Young Park, Do-Hyung Kim