Abstract: A three-dimensional semiconductor device may comprise a first cell region, a second cell region, and a via plug region disposed between the first cell region and the second cell region; a word line stack disposed in the first cell region, the via plug region, and the second cell region, the word line stack including a plurality of word lines and a plurality of interlayer insulating layers which are alternately stacked; and a plurality of via plugs exclusively connected to the plurality of the word lines, respectively, by vertically penetrating through the word line stack in the via plug region. The via plugs may have an arrangement of a zigzag pattern in a row direction from a top view. The diameters of the via plugs may increase in the row direction.

Abstract: A semiconductor device may include a first memory block including at least one first string that is connected between at least one first bit line and a first common source line, a second memory block including at least one second string that is connected between at least one second bit line and a second common source line, and a bit line connection circuit connected between the first bit line and the second bit line and configured to electrically connect or separate the first bit line and the second bit line.

Abstract: A semiconductor device may include: a capacitor including a first source electrode, a second source electrode connected in common to a plurality of second access lines, each of the second access lines spaced apart from one another and located on different layers, and a first channel structure located on the first source electrode and penetrating through the plurality of second access lines; and at least one cell string located between a source line and a first access line, the at least one cell string including a second channel structure penetrating through the plurality of second access lines, the plurality of second access lines electrically separated from each other.

Abstract: A semiconductor memory device includes a stack including a plurality of conductive layers and a plurality of first interlayer insulating layers which are alternately stacked on a first substrate; a plurality of stepped grooves defined at different depths in the stack; and an opening vertically passing through the stack and formed integrally with one of the plurality of stepped grooves, wherein the opening includes a step on a sidewall, and wherein the step has a height the same as a difference in depth between two stepped grooves of the plurality of stepped grooves.

Abstract: A semiconductor device includes a first connection pattern; a bit line disposed over the first connection pattern in a vertical direction; and a bit-line contact pad, disposed in a first layer between the bit line and the first connection pattern to electrically couple the bit line to the first connection pattern, and formed as an island when viewed along the vertical direction. A predetermined number of the bit-line contact pads are spaced apart from each other by a predetermined distance in a first direction, when viewed along the vertical direction.

Abstract: A substrate processing apparatus may include a vacuum chamber, a substrate supporting unit disposed at lower portion of an inside of the vacuum chamber, and an electric field forming unit forming an electric field inside the vacuum chamber. The electric field forming unit may include an upper electrode disposed at an upper portion of the inside of the vacuum chamber, a lower electrode disposed in the substrate supporting unit, and a middle electrode disposed between the upper electrode and the lower electrode.

Abstract: A semiconductor memory device includes a first stack including a plurality of conductive layers and a plurality of first interlayer insulating layers alternately stacked on a substrate; a second stack including a plurality of sacrificial layers and a plurality of second interlayer insulating layers alternately stacked on the substrate; a plurality of stepped grooves defined at different depths in the first stack; and an opening defined in the second stack, and having, on a sidewall thereof, a plurality of steps which have the same heights as differences in depth between the plurality of stepped grooves.

Abstract: A semiconductor device includes a first connection pattern; a bit line disposed over the first connection pattern in a vertical direction; and a bit-line contact pad, disposed in a first layer between the bit line and the first connection pattern to electrically couple the bit line to the first connection pattern, and formed as an island when viewed along the vertical direction. A predetermined number of the bit-line contact pads are spaced apart from each other by a predetermined distance in a first direction, when viewed along the vertical direction.

Abstract: A substrate processing apparatus may include a vacuum chamber, a substrate supporting unit disposed at lower portion of an inside of the vacuum chamber, and an electric field forming unit forming an electric field inside the vacuum chamber. The electric field forming unit may include an upper electrode disposed at an upper portion of the inside of the vacuum chamber, a lower electrode disposed in the substrate supporting unit, and a middle electrode disposed between the upper electrode and the lower electrode.

Abstract: A method for manufacturing a semiconductor device comprises: forming isolation layers in a front surface of an upper wafer substrate; forming a through hole that exposes one of the isolation layers, through the upper wafer substrate from a back surface of the upper wafer substrate; forming a first dielectric layer that fills the through hole; defining a lower wafer including a lower wafer substrate, a second dielectric layer defined on the lower wafer substrate, and a first wiring line disposed in the second dielectric layer; bonding a top surface of the second dielectric layer and a bottom surface of the first dielectric layer; forming a third dielectric layer on the front surface of the upper wafer substrate; forming a through via that passes through the third dielectric layer, the one isolation layer, the first dielectric layer; and forming a second wiring line coupled to the through via.

Abstract: A memory device includes a cell wafer including a memory cell array; and a peripheral wafer including a row control circuit, a column control circuit and a peripheral circuit which control the memory cell array, and stacked on and bonded to the cell wafer in a first direction. The peripheral wafer includes a first substrate having a first surface and a second surface which face away from each other in the first direction; a first logic structure disposed on the first surface of the first substrate, and including the row control circuit and the column control circuit; and a second logic structure disposed on the second surface of the first substrate, and including the peripheral circuit.

Abstract: A method for manufacturing a three-dimensional memory device comprises: forming a first pre-stack by alternately stacking a plurality of first interlayer dielectric layers and a plurality of first sacrificial layers in a vertical direction; forming, in the first pre-stack, a first staircase part; forming a plurality of first vertical vias, which pass through the first staircase part, and a plurality of second vertical vias that pass through a first coupling part of the first pre-stack; forming a second pre-stack by alternately stacking a plurality of second interlayer dielectric layers and a plurality of second sacrificial layers on the first pre-stack; forming, in the second pre-stack, a second staircase part; forming a plurality of third vertical vias and a plurality of fourth vertical vias; and replacing the first and second sacrificial layers with an electrode material.

Abstract: A semiconductor device includes a gate structure including a first select line, a second select line, a first wordline, a second wordline, and a third select line. The semiconductor device also includes a first channel layer passing through the second wordline and the third select line. The semiconductor device further includes a second channel layer passing through the first wordline and the first select line, the second channel layer connected to the first channel layer, and a third channel layer passing through the first wordline and the second select line, the third channel layer connected to the first channel layer. The semiconductor device additionally includes an isolation structure that isolates the second channel layer from the third channel layer.

Abstract: A method for manufacturing a semiconductor device comprises: forming isolation layers in a front surface of an upper wafer substrate; forming a through hole that exposes one of the isolation layers, through the upper wafer substrate from a back surface of the upper wafer substrate; forming a first dielectric layer that fills the through hole; defining a lower wafer including a lower wafer substrate, a second dielectric layer defined on the lower wafer substrate, and a first wiring line disposed in the second dielectric layer; bonding a top surface of the second dielectric layer and a bottom surface of the first dielectric layer; forming a third dielectric layer on the front surface of the upper wafer substrate; forming a through via that passes through the third dielectric layer, the one isolation layer, the first dielectric layer; and forming a second wiring line coupled to the through via.

Abstract: A unit page buffer block includes first to fourth page buffer pairs. Each of the page buffer pairs includes a common column decoder block; and an upper page buffer stage and a lower page buffer stage electrically and commonly connected to the common column decoder block. Each of the upper page buffer stages includes an upper selection block; an upper latch block; and an upper cache block. Each of the lower page buffer stage includes a lower selection block; a lower latch block; and a lower cache block. Each of the upper selection blocks includes first to fourth sub-selection blocks. Each of the upper and lower latch blocks includes first to twelfth upper sub-latch blocks. Each of the upper and lower cache blocks includes first to twelfth upper sub-cache blocks. Each of the common column decoder block includes first to third sub-common column decoder blocks arranged in a row direction.

Abstract: A memory device includes a plurality of bit lines extending in a first direction and arranged in a second direction; and a cell region including a plane which is coupled to the plurality of bit lines, wherein the plane is divided into a plurality of memory groups each including a plurality of partial pages to be disposed in a plurality of rows in the first direction.

Abstract: A three-dimensional memory device includes a lower stack and an upper stack stacked one on the other, and each including a plurality of word lines which are stacked alternately with a plurality of interlayer dielectric layers, wherein each of the lower stack and the upper stack includes a first cell part, a second cell part, a coupling part which couples the first cell part and the second cell part, and a staircase part which extends parallel to the coupling part from the first cell part and in which pad areas of the word lines are disposed in a stepwise manner, and wherein the coupling part of the upper stack is disposed to overlap with the staircase part of the lower stack, and the staircase part of the upper stack is disposed to overlap with the coupling part of the lower stack.

Abstract: A three-dimensional semiconductor device may comprise a first cell region, a second cell region, and a via plug region disposed between the first cell region and the second cell region; a word line stack disposed in the first cell region, the via plug region, and the second cell region, the word line stack including a plurality of word lines and a plurality of interlayer insulating layers which are alternately stacked; and a plurality of via plugs exclusively connected to the plurality of the word lines, respectively, by vertically penetrating through the word line stack in the via plug region. The via plugs may have an arrangement of a zigzag pattern in a row direction from a top view. The diameters of the via plugs may increase in the row direction.

Abstract: A memory may include a first wafer, and a second wafer stacked on and bonded to the first wafer. The first wafer may include a cell structure including a memory cell array; and a first logic structure disposed under the cell structure, and including a row control circuit. The second wafer may include a second logic structure including a column control circuit.

Abstract: A method for manufacturing a three-dimensional memory device comprises: forming a first pre-stack by alternately stacking a plurality of first interlayer dielectric layers and a plurality of first sacrificial layers in a vertical direction; forming, in the first pre-stack, a first staircase part; forming a plurality of first vertical vias, which pass through the first staircase part, and a plurality of second vertical vias that pass through a first coupling part of the first pre-stack; forming a second pre-stack by alternately stacking a plurality of second interlayer dielectric layers and a plurality of second sacrificial layers on the first pre-stack; forming, in the second pre-stack, a second staircase part; forming a plurality of third vertical vias and a plurality of fourth vertical vias; and replacing the first and second sacrificial layers with an electrode material.