Patents by Inventor Sung-man Whang
Sung-man Whang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240096894Abstract: A semiconductor device includes a first semiconductor layer having first and second regions, a plurality of first channel layers spaced apart from each other in a vertical direction on the first region of the first semiconductor layer, a first gate electrode surrounding the plurality of first channel layers, a plurality of second channel layers spaced apart from one another in the vertical direction on the second region of the first semiconductor layer, and a second gate electrode surrounding the plurality of second channel layers, wherein each of the plurality of first channel layers has a first crystallographic orientation, and each of the plurality of second channel layers has a second crystallographic orientation different from the first crystallographic orientation, and wherein a thickness of each of the plurality of first channel layers is different from a thickness of each of the plurality of second channel layers.Type: ApplicationFiled: November 28, 2023Publication date: March 21, 2024Inventors: Woo Cheol SHIN, Myung Gil KANG, Sadaaki MASUOKA, Sang Hoon LEE, Sung Man WHANG
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Patent number: 11862639Abstract: A semiconductor device includes a first semiconductor layer having first and second regions, a plurality of first channel layers spaced apart from each other in a vertical direction on the first region of the first semiconductor layer, a first gate electrode surrounding the plurality of first channel layers, a plurality of second channel layers spaced apart from one another in the vertical direction on the second region of the first semiconductor layer, and a second gate electrode surrounding the plurality of second channel layers, wherein each of the plurality of first channel layers has a first crystallographic orientation, and each of the plurality of second channel layers has a second crystallographic orientation different from the first crystallographic orientation, and wherein a thickness of each of the plurality of first channel layers is different from a thickness of each of the plurality of second channel layers.Type: GrantFiled: August 24, 2022Date of Patent: January 2, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Woo Cheol Shin, Myung Gil Kang, Sadaaki Masuoka, Sang Hoon Lee, Sung Man Whang
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Patent number: 11705503Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, a gate spacer on a sidewall of the gate electrode, an active pattern penetrating the gate electrode and the gate spacer, and an epitaxial pattern contacting the active pattern and the gate spacer. The gate electrode extends in a first direction. The gate spacer includes a semiconductor material layer. The active pattern extends in a second direction crossing the first direction.Type: GrantFiled: September 30, 2020Date of Patent: July 18, 2023Inventors: Jin Bum Kim, MunHyeon Kim, Hyoung Sub Kim, Tae Jin Park, Kwan Heum Lee, Chang Woo Noh, Maria Toledano Lu Que, Hong Bae Park, Si Hyung Lee, Sung Man Whang
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Publication number: 20220406779Abstract: A semiconductor device includes a first semiconductor layer having first and second regions, a plurality of first channel layers spaced apart from each other in a vertical direction on the first region of the first semiconductor layer, a first gate electrode surrounding the plurality of first channel layers, a plurality of second channel layers spaced apart from one another in the vertical direction on the second region of the first semiconductor layer, and a second gate electrode surrounding the plurality of second channel layers, wherein each of the plurality of first channel layers has a first crystallographic orientation, and each of the plurality of second channel layers has a second crystallographic orientation different from the first crystallographic orientation, and wherein a thickness of each of the plurality of first channel layers is different from a thickness of each of the plurality of second channel layers.Type: ApplicationFiled: August 24, 2022Publication date: December 22, 2022Inventors: Woo Cheol SHIN, Myung Gil KANG, Sadaaki MASUOKA, Sang Hoon LEE, Sung Man WHANG
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Patent number: 11437377Abstract: A semiconductor device includes a first semiconductor layer having first and second regions, a plurality of first channel layers spaced apart from each other in a vertical direction on the first region of the first semiconductor layer, a first gate electrode surrounding the plurality of first channel layers, a plurality of second channel layers spaced apart from one another in the vertical direction on the second region of the first semiconductor layer, and a second gate electrode surrounding the plurality of second channel layers, wherein each of the plurality of first channel layers has a first crystallographic orientation, and each of the plurality of second channel layers has a second crystallographic orientation different from the first crystallographic orientation, and wherein a thickness of each of the plurality of first channel layers is different from a thickness of each of the plurality of second channel layers.Type: GrantFiled: September 24, 2020Date of Patent: September 6, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Woo Cheol Shin, Myung Gil Kang, Sadaaki Masuoka, Sang Hoon Lee, Sung Man Whang
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Publication number: 20210020638Abstract: A semiconductor device includes a first semiconductor layer having first and second regions, a plurality of first channel layers spaced apart from each other in a vertical direction on the first region of the first semiconductor layer, a first gate electrode surrounding the plurality of first channel layers, a plurality of second channel layers spaced apart from one another in the vertical direction on the second region of the first semiconductor layer, and a second gate electrode surrounding the plurality of second channel layers, wherein each of the plurality of first channel layers has a first crystallographic orientation, and each of the plurality of second channel layers has a second crystallographic orientation different from the first crystallographic orientation, and wherein a thickness of each of the plurality of first channel layers is different from a thickness of each of the plurality of second channel layers.Type: ApplicationFiled: September 24, 2020Publication date: January 21, 2021Inventors: Woo Cheol SHIN, Myung Gil KANG, Sadaaki MASUOKA, Sang Hoon LEE, Sung Man WHANG
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Publication number: 20210013324Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, a gate spacer on a sidewall of the gate electrode, an active pattern penetrating the gate electrode and the gate spacer, and an epitaxial pattern contacting the active pattern and the gate spacer. The gate electrode extends in a first direction. The gate spacer includes a semiconductor material layer. The active pattern extends in a second direction crossing the first direction.Type: ApplicationFiled: September 30, 2020Publication date: January 14, 2021Inventors: Jin Bum KIM, MunHyeon KIM, Hyoung Sub KIM, Tae Jin PARK, Kwan Heum LEE, Chang Woo NOH, Maria TOLEDANO LU QUE, Hong Bae PARK, Si Hyung LEE, Sung Man WHANG
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Patent number: 10833085Abstract: A semiconductor device includes a first semiconductor layer having first and second regions, a plurality of first channel layers spaced apart from each other in a vertical direction on the first region of the first semiconductor layer, a first gate electrode surrounding the plurality of first channel layers, a plurality of second channel layers spaced apart from one another in the vertical direction on the second region of the first semiconductor layer, and a second gate electrode surrounding the plurality of second channel layers, wherein each of the plurality of first channel layers has a first crystallographic orientation, and each of the plurality of second channel layers has a second crystallographic orientation different from the first crystallographic orientation, and wherein a thickness of each of the plurality of first channel layers is different from a thickness of each of the plurality of second channel layers.Type: GrantFiled: June 13, 2019Date of Patent: November 10, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Woo Cheol Shin, Myung Gil Kang, Sadaaki Masuoka, Sang Hoo Lee, Sung Man Whang
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Publication number: 20200219879Abstract: A semiconductor device includes a first semiconductor layer having first and second regions, a plurality of first channel layers spaced apart from each other in a vertical direction on the first region of the first semiconductor layer, a first gate electrode surrounding the plurality of first channel layers, a plurality of second channel layers spaced apart from one another in the vertical direction on the second region of the first semiconductor layer, and a second gate electrode surrounding the plurality of second channel layers, wherein each of the plurality of first channel layers has a first crystallographic orientation, and each of the plurality of second channel layers has a second crystallographic orientation different from the first crystallographic orientation, and wherein a thickness of each of the plurality of first channel layers is different from a thickness of each of the plurality of second channel layers.Type: ApplicationFiled: June 13, 2019Publication date: July 9, 2020Inventors: Woo Cheol SHIN, Myung Gil KANG, Sadaaki MASUOKA, Sang Hoo LEE, Sung Man WHANG
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Patent number: 10396205Abstract: An integrated circuit device includes a base burying insulating film covering a lower side wall of a fin-type active region on a substrate, an isolation pattern having a top surface higher than a top surface of the base burying insulating film, and a gate line covering a channel section of the fin-type active region. The gate line has an upper gate covering an upper portion of the channel section and a lower gate protruding from the upper gate toward the substrate and filling a space between a lower side wall of the channel section and an upper side wall of the isolation pattern.Type: GrantFiled: April 12, 2018Date of Patent: August 27, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Mun-hyeon Kim, Sung-man Whang, Chang-woo Noh, Dong-won Kim, Han-su Oh
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Publication number: 20190198639Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, a gate spacer on a sidewall of the gate electrode, an active pattern penetrating the gate electrode and the gate spacer, and an epitaxial pattern contacting the active pattern and the gate spacer. The gate electrode extends in a first direction. The gate spacer includes a semiconductor material layer. The active pattern extends in a second direction crossing the first direction.Type: ApplicationFiled: July 17, 2018Publication date: June 27, 2019Inventors: Jin Bum KIM, MunHyeon KIM, Hyoung Sub KIM, Tae Jin PARK, Kwan Heum LEE, Chang Woo NOH, Maria TOLEDANO LU QUE, Hong Bae PARK, Si Hyung LEE, Sung Man WHANG
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Publication number: 20190097054Abstract: An integrated circuit device includes a base burying insulating film covering a lower side wall of a fin-type active region on a substrate, an isolation pattern having a top surface higher than a top surface of the base burying insulating film, and a gate line covering a channel section of the fin-type active region. The gate line has an upper gate covering an upper portion of the channel section and a lower gate protruding from the upper gate toward the substrate and filling a space between a lower side wall of the channel section and an upper side wall of the isolation pattern.Type: ApplicationFiled: April 12, 2018Publication date: March 28, 2019Inventors: Mun-hyeon KIM, Sung-man Whang, Chang-woo NOH, Dong-won KIM, Han-su OH
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Patent number: 9905645Abstract: A vertical field effect transistor is provided as follows. A substrate has a lower drain and a lower source arranged along a first direction in parallel to an upper surface of the substrate. A fin structure is disposed on the substrate and extended vertically from the upper surface of the substrate. The fin structure includes a first end portion and a second end portion arranged along the first direction. A bottom surface of a first end portion of the fin structure and a bottom surface of a second end portion of the fin structure overlap the lower drain and the lower source, respectively. The fin structure includes a sidewall having a lower sidewall region, a center sidewall region and an upper sidewall region. A gate electrode surrounds the center side sidewall region of the fin structure.Type: GrantFiled: September 2, 2016Date of Patent: February 27, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Myung Gil Kang, Seung Han Park, Yong Hee Park, Sang Hoon Baek, Sang Woo Lee, Keon Yong Cheon, Sung Man Whang
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Publication number: 20170345897Abstract: A vertical field effect transistor is provided as follows. A substrate has a lower drain and a lower source arranged along a first direction in parallel to an upper surface of the substrate. A fin structure is disposed on the substrate and extended vertically from the upper surface of the substrate. The fin structure includes a first end portion and a second end portion arranged along the first direction. A bottom surface of a first end portion of the fin structure and a bottom surface of a second end portion of the fin structure overlap the lower drain and the lower source, respectively. The fin structure includes a sidewall having a lower sidewall region, a center sidewall region and an upper sidewall region. A gate electrode surrounds the center side sidewall region of the fin structure.Type: ApplicationFiled: September 2, 2016Publication date: November 30, 2017Inventors: Myung Gil KANG, Seung Han PARK, Yong Hee PARK, Sang Hoon BAEK, Sang Woo LEE, Keon Yong CHEON, Sung Man WHANG
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Patent number: 6541328Abstract: In a method of fabricating a metal oxide semiconductor (MOS) transistor with a lightly doped drain (LDD) structure without spacers, gate electrodes and spacers are formed on a semiconductor substrate. A high density source/drain region is formed using the gate electrodes and the spacers as masks. A low density source/drain region is formed after removing the spacers. It is possible to reduce the thermal stress of the low density source/drain region by forming the high density source/drain region before the low density source/drain region is formed and to increase an area, in which suicide is formed, by forming a structure without spacers. Also, it is possible to simplify processes of fabricating a complementary metal oxide semiconductor (CMOS) LDD transistor by reducing the number of photoresist pattern forming processes in the method.Type: GrantFiled: November 2, 2001Date of Patent: April 1, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-man Whang, Hyung-moo Park, Dong-cho Maeng, Hyae-Ryoung Lee, Ho-woo Park
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Publication number: 20020115258Abstract: In a method of fabricating a metal oxide semiconductor (MOS) transistor with a lightly doped drain (LDD) structure without spacers, gate electrodes and spacers are formed on a semiconductor substrate. A high density source/drain region is formed using the gate electrodes and the spacers as masks. A low density source/drain region is formed after removing the spacers. It is possible to reduce the thermal stress of the low density source/drain region by forming the high density source/drain region before the low density source/drain region is formed and to increase an area, in which silicide is formed, by forming a structure without spacers. Also, it is possible to simplify processes of fabricating a complementary metal oxide semiconductor (CMOS) LDD transistor by reducing the number of photoresist pattern forming processes in the method.Type: ApplicationFiled: November 2, 2001Publication date: August 22, 2002Applicant: Samsung Electronics Co., Ltd.Inventors: Sung-man Whang, Hyung-moo Park, Dong-cho Maeng, Hyae-Ryoung Lee, Ho-woo Park