Abstract: A battery module includes: a battery cell assembly having a plurality of battery cells; a top plate configured to cover an upper side of the battery cell assembly; a bottom plate configured to cover a lower side of the battery cell assembly; a sensing assembly disposed to cover a front side and a rear side of the battery cell assembly; a pair of side plates disposed at side surfaces, respectively, of the battery cell assembly; and a pair of compression pads disposed between the pair of side plates and the battery cell assembly, respectively.

Abstract: A robotic prosthetic foot according to the present disclosure includes a coupling module having an upper portion to which a limb part of a user is coupled, a prosthetic foot module configured to be coupled to a lower portion of the coupling module and support a load of the user to enable the user to walk, and a joint module provided at the coupling module to enable the prosthetic foot module to rotate, wherein the joint module includes an elastic unit configured to compress and expand due to the prosthetic foot module rotating as the user walks and generate an elastic restoring force to facilitate the rotation of the prosthetic foot module.

Abstract: Disclosed is a method for manufacturing a functionalized separator having a zwitterionic coating thereon. The method includes preparing a porous separator; coating a linker on a surface of the porous separator; and chemically reacting zwitterions with the linker such the zwitterions are grafted to the linker on the surface of the separator. The zwitterions grafted to the linker acts as a monolayer to functionalize the surface of the separator. The functionalized separator may disallow elution of polysulfide compound in a lithium-sulfur battery. Further, the functionalized separator may increase ion conductivity of electrolyte of the lithium-sulfur battery and thus ensure high output characteristics.

Abstract: Disclosed is a method for manufacturing a functionalized separator having a zwitterionic coating thereon. The method includes preparing a porous separator; coating a linker on a surface of the porous separator; and chemically reacting zwitterions with the linker such the zwitterions are grafted to the linker on the surface of the separator. The zwitterions grafted to the linker acts as a monolayer to functionalize the surface of the separator. The functionalized separator may disallow elution of polysulfide compound in a lithium-sulfur battery. Further, the functionalized separator may increase ion conductivity of electrolyte of the lithium-sulfur battery and thus ensure high output characteristics.

Abstract: The multi-rotor type unmanned aerial vehicle includes: a main body including the battery module and the control module; a plurality of frames connected to a side surface of the main body and extending therefrom; a first motor connected to a distal end of each of the frames; and a drive unit connected to the first motor, wherein the drive unit includes a rotary frame and a stationary frame each having a circular shape and connected to each other in the form of a gyroscope, a second motor supported at the center of the rotatable frame, and a propeller connected to the second motor, and a vector of thrust generated by rotation of the propeller is variable according to rotation of the first and second motors.

Abstract: A mask including: a transparent substrate and a light blocking layer thereon. The transparent substrate includes a first transmitting portion and a second transmitting portion each configured to pass light, and a light blocking portion configured to block light. The first transmitting portion includes a first transmitting region configured to pass light and a first light blocking region configured to block light, and area centers of the first transmitting region and the first light blocking region substantially coincide. The second transmitting portion includes a second transmitting region configured to pass light and a second light blocking region configured to block light, and area centers of the second transmitting region and the second light blocking region substantially coincide, so that the first transmitting portion is configured to pass light of a greater intensity and the second transmitting portion is configured to pass light of a lesser intensity.

Abstract: A manufacturing process of a circuit substrate is provided. A conductive structure including a first patterned conductive layer, a first dielectric layer, a second dielectric layer, a first conductive layer, and a second conductive layer is provided. The first dielectric layer and the second dielectric layer are respectively disposed on two opposite surfaces of the first patterned conductive layer. The first conductive layer and the second conductive layer are respectively disposed on the first dielectric layer and the second dielectric layer. The first dielectric layer is between the first patterned conductive layer and the first conductive layer. The second dielectric layer is between the first patterned conductive layer and the second conductive layer. A conductive via is formed at the conductive structure. The first conductive layer and the second conductive layer are patterned to respectively form a second patterned conductive layer and a third patterned conductive layer.

Abstract: Substrate test probing equipment having a force-receiving pattern for a probe card and a forcing part for a test head, and methods of using the same, in which with the force-receiving pattern for the probe card and the forcing part for the test head, thermal expansion and contraction of the probe card can be suppressed when the semiconductor substrate is being tested at high and low temperatures. To this end, to substrate test probing equipment having a substrate mover, a probe card, and a test head is prepared, in which the test head has a forcing part and the probe card has a force-receiving plate. A semiconductor substrate is placed on the substrate mover to be electrically connected with the probe card. The semiconductor substrate is electrically tested by the probe card and the test head. When the semiconductor substrate is being tested, the forcing part of the test head is brought into contact with the force-receiving pattern of the probe card.

Abstract: An integrated circuit is provided comprising a first NMOS transistor; a first PMOS transistor; a second NMOS transistor; a second PMOS transistor; a first bias voltage node coupled to a first source/drain of the first NMOS transistor; a second bias voltage node coupled to a first source/drain of the second PMOS; a third bias voltage node coupled to a gate of the first PMOS transistor; a fourth bias voltage node coupled to a gate of the second NMOS transistor; a pull-up node coupling a second source/drain of the first NMOS transistor to a first source/drain of the first PMOS transistor; a pull-down node coupling a second source/drain of the second PMOS transistor to a first source/drain of the second NMOS transistor; an input node; a storage node coupling a second source/drain of the first PMOS transistor to a second source/drain of the second NMOS transistor; an output node; an input switch coupled to controllably communicate an input data value from the input node to a gate of the first NMOS transistor and t

Abstract: A multi probe card unit, a probe test device including the multi probe card unit, and methods of fabricating and using the same are provided. The multi probe card unit may include at least one probe card including a first plurality of probes on a first surface of the at least one probe card and a second plurality of probes on a second surface of the at least one probe card.

Abstract: Substrate test probing equipment having a force-receiving pattern for a probe card and a forcing part for a test head, and methods of using the same, in which with the force-receiving pattern for the probe card and the forcing part for the test head, thermal expansion and contraction of the probe card can be suppressed when the semiconductor substrate is being tested at high and low temperatures. To this end, to substrate test probing equipment having a substrate mover, a probe card, and a test head is prepared, in which the test head has a forcing part and the probe card has a force-receiving plate. A semiconductor substrate is placed on the substrate mover to be electrically connected with the probe card. The semiconductor substrate is electrically tested by the probe card and the test head. When the semiconductor substrate is being tested, the forcing part of the test head is brought into contact with the force-receiving pattern of the probe card.

Abstract: An integrated circuit is provided comprising a latch circuit including, a first inverter including a first high threshold voltage PMOS transistor and a first high threshold voltage NMOS transistor with a first data node comprising interconnected source/drains (S/D) of the first PMOS and NMOS transistors; a second inverter including a second high threshold voltage PMOS transistor and a second high threshold voltage NMOS transistor with a second data node comprising interconnected source/drains (S/D) of the second PMOS and NMOS transistors; wherein the gates of the first PMOS and first NMOS transistors are coupled to the second data node; wherein the gates of the second PMOS and second NMOS transistors are coupled to the first data node; a first low threshold voltage access transistor including a first S/D coupled to the first data node and to the gate of the second PMOS transistor and to the gate of the second NMOS transistor and including a second S/D coupled to a first data access node and including a gate c

Abstract: An integrated circuit is provided which includes a multi-state circuit with a first PMOS transistor and a first NMOS transistor. In an active mode, the multi-state circuit is operable to switch between a first state in which the first PMOS transistor is turned on and the first NMOS transistor is turned off and a second state in which the first PMOS transistor is turned off and the first NMOS transistor is turned on. A power source NMOS transistor has a drain connected to a supply voltage terminal and has a source connected to a source of the first PMOS transistor. A power source PMOS transistor has a drain connected to a an effective ground terminal and has a source connected to a source of the first NMOS transistor.

Abstract: A donut-type parallel probe card comprises a main substrate and a plurality of probing blocks installed on a surface of the main substrate, wherein each probe block comprises a plurality of probes. The probing blocks are arranged to fill a first region having an oval shape and surrounding a second region, and no probing blocks are arranged within the second region.

Abstract: A probe card for that may be used to test a plurality of semiconductor chips formed on a wafer. The probe card may include a substrate; a plurality of probe blocks that form a pattern corresponding to the pattern formed by the plurality of semiconductor chips formed on the wafer; and a plurality of probe needles formed in the probe blocks and arranged in a pattern corresponding to a plurality of pads formed in the plurality of semiconductor chips. The use of the probe card may decrease the testing time for the wafer.

Abstract: An integrated circuit is provided comprising a first NMOS transistor; a first PMOS transistor; a second NMOS transistor; a second PMOS transistor; a first bias voltage node coupled to a first source/drain of the first NMOS transistor; a second bias voltage node coupled to a first source/drain of the second PMOS; a third bias voltage node coupled to a gate of the first PMOS transistor; a fourth bias voltage node coupled to a gate of the second NMOS transistor; a pull-up node coupling a second source/drain of the first NMOS transistor to a first source/drain of the first PMOS transistor; a pull-down node coupling a second source/drain of the second PMOS transistor to a first source/drain of the second NMOS transistor; an input node; a storage node coupling a second source/drain of the first PMOS transistor to a second source/drain of the second NMOS transistor; an output node; an input switch coupled to controllably communicate an input data value from the input node to a gate of the first NMOS transistor and t

Abstract: An integrated circuit is provided comprising a first NMOS transistor; a first PMOS transistor; a second NMOS transistor; a second PMOS transistor; a first bias voltage node coupled to a first source/drain of the first NMOS transistor; a second bias voltage node coupled to a first source/drain of the second PMOS; a third bias voltage node coupled to a gate of the first PMOS transistor; a fourth bias voltage node coupled to a gate of the second NMOS transistor; a pull-up node coupling a second source/drain of the first NMOS transistor to a first source/drain of the first PMOS transistor; a pull-down node coupling a second source/drain of the second PMOS transistor to a first source/drain of the second NMOS transistor; an input node; a storage node coupling a second source/drain of the first PMOS transistor to a second source/drain of the second NMOS transistor; an output node; an input switch coupled to controllably communicate an input data value from the input node to a gate of the first NMOS transistor and t

Abstract: Methods and circuits are described for reducing power consumption within digital logic circuits by blocking the passage of clock signal transitions to the logic circuits when the clock signal would not produce a desired change of state within the logic circuit, such as at inputs, intermediary nodes, outputs, or combinations. By way of example, the incoming clock is blocked if a given set of logic inputs will not result in an output change of state if a clock signal transition were to be received. By way of further example, the incoming clock is blocked in a data flip-flop if the input signal matches the output signal, such that receipt of a clock transition would not produce a desired change of state in the latched output. The invention may be utilized for creating lower power combinatorial and/or sequential logic circuit stages subject to less unproductive charging and discharging of gate capacitances.

Abstract: An integrated circuit is provided which includes a multi-state circuit with a first PMOS transistor and a first NMOS transistor. In an active mode, the multi-state circuit is operable to switch between a first state in which the first PMOS transistor is turned on and the first NMOS transistor is turned off and a second state in which the first PMOS transistor is turned off and the first NMOS transistor is turned on. A power source NMOS transistor has a drain connected to a supply voltage terminal and has a source connected to a source of the first PMOS transistor. A power source PMOS transistor has a drain connected to a an effective ground terminal and has a source connected to a source of the first NMOS transistor.

Abstract: An integrated circuit is provided comprising a latch circuit including, a first inverter including a first high threshold voltage PMOS transistor and a first high threshold voltage NMOS transistor with a first data node comprising interconnected source/drains (S/D) of the first PMOS and NMOS transistors; a second inverter including a second high threshold voltage PMOS transistor and a second high threshold voltage NMOS transistor with a second data node comprising interconnected source/drains (S/D) of the second PMOS and NMOS transistors; wherein the gates of the first PMOS and first NMOS transistors are coupled to the second data node; wherein the gates of the second PMOS and second NMOS transistors are coupled to the first data node; a first low threshold voltage access transistor including a first S/D coupled to the first data node and to the gate of the second PMOS transistor and to the gate of the second NMOS transistor and including a second S/D coupled to a first data access node and including a gate c