Patents by Inventor Sung-taeg Kang
Sung-taeg Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240008279Abstract: A semiconductor device and method of fabricating the same are disclosed. The method includes depositing a polysilicon gate layer over a gate dielectric formed over a surface of a substrate in a peripheral region, forming a dielectric layer over the polysilicon gate layer and depositing a height-enhancing (HE) film over the dielectric layer. The HE film, the dielectric layer, the polysilicon gate layer and the gate dielectric are then patterned for a high-voltage Field Effect Transistor (HVFET) gate to be formed in the peripheral region. A high energy implant is performed to form at least one lightly doped region in a source or drain region in the substrate adjacent to the HVFET gate. The HE film is then removed, and a low voltage (LV) logic FET formed on the substrate in the peripheral region. In one embodiment, the LV logic FET is a high-k metal-gate logic FET.Type: ApplicationFiled: June 26, 2023Publication date: January 4, 2024Applicant: Cypress Semiconductor CorporationInventors: Chun Chen, James Pak, Unsoon KIM, Inkuk Kang, Sung-Taeg Kang, Kuo Tung Chang
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Publication number: 20230317180Abstract: The gap width in a threshold voltage (Vt) distribution for a 3D NAND Flash cell is improved by performing touchup program on a selected portion of the word lines in a block after all of the word lines in the block have been programmed.Type: ApplicationFiled: June 7, 2023Publication date: October 5, 2023Inventors: Rifat FERDOUS, Sung-Taeg KANG, Golnaz KARBASIAN, Ali KHAKIFIROOZ, Rohit S. SHENOY
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Patent number: 11690227Abstract: A semiconductor device and method of fabricating the same are disclosed. The method includes depositing a polysilicon gate layer over a gate dielectric formed over a surface of a substrate in a peripheral region, forming a dielectric layer over the polysilicon gate layer and depositing a height-enhancing (HE) film over the dielectric layer. The HE film, the dielectric layer, the polysilicon gate layer and the gate dielectric are then patterned for a high-voltage Field Effect Transistor (HVFET) gate to be formed in the peripheral region. A high energy implant is performed to form at least one lightly doped region in a source or drain region in the substrate adjacent to the HVFET gate. The HE film is then removed, and a low voltage (LV) logic FET formed on the substrate in the peripheral region. In one embodiment, the LV logic FET is a high-k metal-gate logic FET.Type: GrantFiled: May 18, 2021Date of Patent: June 27, 2023Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Chun Chen, James Pak, Unsoon Kim, Inkuk Kang, Sung-Taeg Kang, Kuo Tung Chang
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Patent number: 11587874Abstract: Apparatus, systems, or methods for a memory array having a plurality of word lines. A word line includes at least one word line plate, and the word line plate comprises a first material with a first resistivity. An edge of the word line plate is recessed and filled with a second material having a second resistivity that is lower than the first resistivity. As a result, the total resistance of the word line may be reduced compared to a word line using only the first material with the first resistivity. Other embodiments may also be described and claimed.Type: GrantFiled: February 24, 2020Date of Patent: February 21, 2023Assignee: Intel CorporationInventors: Sung-Taeg Kang, Pranav Kalavade, Owen W. Jungroth, Prasanna Srinivasan
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Publication number: 20220366962Abstract: After reading a 3D (three dimensional) NAND array, the wordlines of the 3D NAND array can be transitioned to ground in a staggered manner. The 3D NAND array includes a 3D stack with multiple wordlines vertically stacked, including a bottom-most wordline, a top-most wordline, and middle wordlines between the bottom-most wordline and the top-most wordline. A controller that controls the reading can set the multiple wordlines to a read voltage for reading operations and then transition a selected wordline of the multiple wordlines from the read voltage to ground prior to transitioning the other wordlines to ground. Thus, the controller will transition the other wordlines from the read voltage to ground after a delay.Type: ApplicationFiled: May 17, 2021Publication date: November 17, 2022Inventors: Rifat FERDOUS, Sung-Taeg KANG, Rohit S. SHENOY, Ali KHAKIFIROOZ, Dipanjan BASU
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Publication number: 20210296343Abstract: A semiconductor device and method of fabricating the same are disclosed. The method includes depositing a polysilicon gate layer over a gate dielectric formed over a surface of a substrate in a peripheral region, forming a dielectric layer over the polysilicon gate layer and depositing a height-enhancing (HE) film over the dielectric layer. The HE film, the dielectric layer, the polysilicon gate layer and the gate dielectric are then patterned for a high-voltage Field Effect Transistor (HVFET) gate to be formed in the peripheral region. A high energy implant is performed to form at least one lightly doped region in a source or drain region in the substrate adjacent to the HVFET gate. The HE film is then removed, and a low voltage (LV) logic FET formed on the substrate in the peripheral region. In one embodiment, the LV logic FET is a high-k metal-gate logic FET.Type: ApplicationFiled: May 18, 2021Publication date: September 23, 2021Applicant: Cypress Semiconductor CorporationInventors: Chun Chen, James Pak, Unsoon KIM, Inkuk Kang, Sung-Taeg Kang, Kuo Tung Chang
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Publication number: 20210265278Abstract: Apparatus, systems, or methods for a memory array having a plurality of word lines. A word line includes at least one word line plate, and the word line plate comprises a first material with a first resistivity. An edge of the word line plate is recessed and filled with a second material having a second resistivity that is lower than the first resistivity. As a result, the total resistance of the word line may be reduced compared to a word line using only the first material with the first resistivity. Other embodiments may also be described and claimed.Type: ApplicationFiled: February 24, 2020Publication date: August 26, 2021Inventors: Sung-Taeg Kang, Pranav Kalavade, Owen W. Jungroth, Prasanna Srinivasan
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Publication number: 20210134811Abstract: Systems and methods of forming such include method, forming a memory gate (MG) stack in a first region, forming a sacrificial polysilicon gate on a high-k dielectric in a second region, wherein the first and second regions are disposed in a single substrate. Then a select gate (SG) may be formed adjacent to the MG stack in the first region of the semiconductor substrate. The sacrificial polysilicon gate may be replaced with a metal gate to form a logic field effect transistor (FET) in the second region. The surfaces of the substrate in the first region and the second region are substantially co-planar.Type: ApplicationFiled: November 20, 2020Publication date: May 6, 2021Applicant: Cypress Semiconductor CorporationInventors: Chun Chen, James Pak, Unsoon Kim, Inkuk Kang, Sung-Taeg Kang, Kuo Tung Chang
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Patent number: 10872898Abstract: Systems and methods of forming such include method, forming a memory gate (MG) stack in a first region, forming a sacrificial polysilicon gate on a high-k dielectric in a second region, wherein the first and second regions are disposed in a single substrate. Then a select gate (SG) may be formed adjacent to the MG stack in the first region of the semiconductor substrate. The sacrificial polysilicon gate may be replaced with a metal gate to form a logic field effect transistor (FET) in the second region. The surfaces of the substrate in the first region and the second region are substantially co-planar.Type: GrantFiled: December 20, 2017Date of Patent: December 22, 2020Assignee: Cypress Semiconductor CorporationInventors: Chun Chen, James Pak, Unsoon Kim, Inkuk Kang, Sung-Taeg Kang, Kuo Tung Chang
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Patent number: 10716822Abstract: Provided are a seed of new soybean cultivar SCEL-1, a plant body of the seed or a part of the plant body, and an extract obtained from the seed.Type: GrantFiled: December 6, 2018Date of Patent: July 21, 2020Assignees: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY, REPUBLIC OF KOREA (MANAGEMENT : RURAL DEVELOPMENT ADMINISTRATION)Inventors: Jung Kyung Moon, Man Soo Choi, Soo Kwon Park, Nam Hee Jeong, Yongsoo Choi, Sungdo Ha, Cheol-Ho Pan, Sung Taeg Kang, Soon Chun Jeong
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Publication number: 20200000866Abstract: Provided are a seed of new soybean cultivar SCEL-1, a plant body of the seed or a part of the plant body, and an extract obtained from the seed.Type: ApplicationFiled: December 6, 2018Publication date: January 2, 2020Applicants: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY, REPUBLIC OF KOREA(MANAGEMENT : RURAL DEVELOPMENT ADMINISTRATION)Inventors: Jung Kyung MOON, Man Soo CHOI, Soo Kwon PARK, Nam Hee JEONG, Yongsoo CHOI, Sungdo HA, Cheol-Ho PAN, Sung Taeg KANG, Soon Chun JEONG
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Patent number: 10497710Abstract: A semiconductor device and method of making the same are disclosed. The semiconductor device includes a metal-gate logic transistor formed in a first region of a substrate, and a non-volatile memory (NVM) cell including a select gate and a memory gate formed in a first recess in a second region of the same substrate, wherein the recess is recessed relative to a first surface of the substrate. The metal-gate logic transistor includes a planarized surface above and substantially parallel to the first surface, and top surfaces of the select gate and memory gate are approximately at or below an elevation of the planarized surface of the metal-gate. Generally, at least one of the top surfaces of the select gate or the memory gate includes a silicide formed thereon. Other embodiments are also disclosed.Type: GrantFiled: October 12, 2017Date of Patent: December 3, 2019Assignee: Cypress Semiconductor CorporationInventors: Sung-Taeg Kang, James Pak, Unsoon Kim, Inkuk Kang, Chun Chen, Kuo-Tung Chang
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Publication number: 20190304990Abstract: A semiconductor device and method of fabricating the same are disclosed. The method includes depositing a polysilicon gate layer over a gate dielectric formed over a surface of a substrate in a peripheral region, forming a dielectric layer over the polysilicon gate layer and depositing a height-enhancing (HE) film over the dielectric layer. The HE film, the dielectric layer, the polysilicon gate layer and the gate dielectric are then patterned for a high-voltage Field Effect Transistor (HVFET) gate to be formed in the peripheral region. A high energy implant is performed to form at least one lightly doped region in a source or drain region in the substrate adjacent to the HVFET gate. The HE film is then removed, and a low voltage (LV) logic FET formed on the substrate in the peripheral region. In one embodiment, the LV logic FET is a high-k metal-gate logic FET.Type: ApplicationFiled: March 4, 2019Publication date: October 3, 2019Applicant: Cypress Semiconductor CorporationInventors: Chun Chen, James Pak, Unsoon KIM, Inkuk Kang, Sung-Taeg Kang, Kuo Tung Chang
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Patent number: 10242996Abstract: A semiconductor device and method of fabricating the same are disclosed. The method includes depositing a polysilicon gate layer over a gate dielectric formed over a surface of a substrate in a peripheral region, forming a dielectric layer over the polysilicon gate layer and depositing a height-enhancing (HE) film over the dielectric layer. The HE film, the dielectric layer, the polysilicon gate layer and the gate dielectric are then patterned for a high-voltage Field Effect Transistor (HVFET) gate to be formed in the peripheral region. A high energy implant is performed to form at least one lightly doped region in a source or drain region in the substrate adjacent to the HVFET gate. The HE film is then removed, and a low voltage (LV) logic FET formed on the substrate in the peripheral region. In one embodiment, the LV logic FET is a high-k metal-gate logic FET.Type: GrantFiled: December 20, 2017Date of Patent: March 26, 2019Assignee: Cypress Semiconductor CorporationInventors: Chun Chen, James Pak, Unsoon Kim, Inkuk Kang, Sung-Taeg Kang, Kuo Tung Chang
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Publication number: 20190027487Abstract: A semiconductor device and method of fabricating the same are disclosed. The method includes depositing a polysilicon gate layer over a gate dielectric formed over a surface of a substrate in a peripheral region, forming a dielectric layer over the polysilicon gate layer and depositing a height-enhancing (HE) film over the dielectric layer. The HE film, the dielectric layer, the polysilicon gate layer and the gate dielectric are then patterned for a high-voltage Field Effect Transistor (HVFET) gate to be formed in the peripheral region. A high energy implant is performed to form at least one lightly doped region in a source or drain region in the substrate adjacent to the HVFET gate. The HE film is then removed, and a low voltage (LV) logic FET formed on the substrate in the peripheral region. In one embodiment, the LV logic FET is a high-k metal-gate logic FET.Type: ApplicationFiled: December 20, 2017Publication date: January 24, 2019Applicant: Cypress Semiconductor CorporationInventors: Chun Chen, James Pak, Unsoon Kim, Inkuk Kang, Sung-Taeg Kang, Kuo Tung Chang
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Publication number: 20190027484Abstract: Systems and methods of forming such include method, forming a memory gate (MG) stack in a first region, forming a sacrificial polysilicon gate on a high-k dielectric in a second region, wherein the first and second regions are disposed in a single substrate. Then a select gate (SG) may be formed adjacent to the MG stack in the first region of the semiconductor substrate. The sacrificial polysilicon gate may be replaced with a metal gate to form a logic field effect transistor (FET) in the second region. The surfaces of the substrate in the first region and the second region are substantially co-planar.Type: ApplicationFiled: December 20, 2017Publication date: January 24, 2019Applicant: Cypress Semiconductor CorporationInventors: Chun Chen, James Pak, Unsoon Kim, Inkuk Kang, Sung-Taeg Kang, Kuo Tung Chang
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Patent number: 10153349Abstract: A method of forming a split gate memory cell structure using a substrate includes forming a gate stack comprising a select gate and a dielectric portion overlying the select gate. A charge storage layer is formed over the substrate including over the gate stack. A first sidewall spacer of conductive material is formed along a first sidewall of the gate stack extending past a top of the select gate. A second sidewall spacer of dielectric material is formed along the first sidewall on the first sidewall spacer. A portion of the first sidewall spacer is silicided using the second sidewall spacer as a mask whereby silicide does not extend to the charge storage layer.Type: GrantFiled: January 24, 2017Date of Patent: December 11, 2018Assignee: NXP USA, Inc.Inventors: Cheong Min Hong, Sung-Taeg Kang
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Publication number: 20180166458Abstract: A semiconductor device and method of making the same are disclosed. The semiconductor device includes a metal-gate logic transistor formed in a first region of a substrate, and a non-volatile memory (NVM) cell including a select gate and a memory gate formed in a first recess in a second region of the same substrate, wherein the recess is recessed relative to a first surface of the substrate. The metal-gate logic transistor includes a planarized surface above and substantially parallel to the first surface, and top surfaces of the select gate and memory gate are approximately at or below an elevation of the planarized surface of the metal-gate. Generally, at least one of the top surfaces of the select gate or the memory gate includes a silicide formed thereon. Other embodiments are also disclosed.Type: ApplicationFiled: October 12, 2017Publication date: June 14, 2018Applicant: Cypress Semiconductor CorporationInventors: Sung-Taeg Kang, James Pak, Unsoon KIM, Inkuk Kang, Chun Chen, Kuo-Tung Chang
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Patent number: 9853039Abstract: A semiconductor device including a non-volatile memory (NVM) cell and method of making the same are disclosed. The semiconductor device includes a metal-gate logic transistor formed on a logic region of a substrate, and the NVM cell integrally formed in a first recess in a memory region of the same substrate, wherein the first recess is recessed relative to a first surface of the substrate in the logic region. Generally, the metal-gate logic transistor further including a planarized surface above and substantially parallel to the first surface of the substrate in the logic region, and the NVM cell is arranged below an elevation of the planarized surface of the metal-gate. In some embodiments, logic transistor is a High-k Metal-gate (HKMG) logic transistor with a gate structure including a metal-gate and a high-k gate dielectric. Other embodiments are also disclosed.Type: GrantFiled: March 29, 2017Date of Patent: December 26, 2017Assignee: Cypress Semiconductor CorporationInventors: Sung-Taeg Kang, James Pak, Unsoon Kim, Inkuk Kang, Chun Chen, Kuo-Tung Chang
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Patent number: 9818755Abstract: A semiconductor device including a non-volatile memory (NVM) cell and method of making the same are disclosed. The semiconductor device includes a metal-gate logic transistor formed on a logic region of a substrate, and the NVM cell integrally formed in a first recess in a memory region of the same substrate, wherein the first recess is recessed relative to a first surface of the substrate in the logic region. Generally, the metal-gate logic transistor further including a planarized surface above and substantially parallel to the first surface of the substrate in the logic region, and the NVM cell is arranged below an elevation of the planarized surface of the metal-gate. In some embodiments, logic transistor is a High-k Metal-gate (HKMG) logic transistor with a gate structure including a metal-gate and a high-k gate dielectric. Other embodiments are also disclosed.Type: GrantFiled: March 29, 2017Date of Patent: November 14, 2017Assignee: Cypress Semiconductor CorporationInventors: Sung-Taeg Kang, James Pak, Unsoon Kim, Inkuk Kang, Chun Chen, Kuo-Tung Chang