Patents by Inventor Sung-taeg Kang

Sung-taeg Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200000866
    Abstract: Provided are a seed of new soybean cultivar SCEL-1, a plant body of the seed or a part of the plant body, and an extract obtained from the seed.
    Type: Application
    Filed: December 6, 2018
    Publication date: January 2, 2020
    Applicants: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY, REPUBLIC OF KOREA(MANAGEMENT : RURAL DEVELOPMENT ADMINISTRATION)
    Inventors: Jung Kyung MOON, Man Soo CHOI, Soo Kwon PARK, Nam Hee JEONG, Yongsoo CHOI, Sungdo HA, Cheol-Ho PAN, Sung Taeg KANG, Soon Chun JEONG
  • Patent number: 10497710
    Abstract: A semiconductor device and method of making the same are disclosed. The semiconductor device includes a metal-gate logic transistor formed in a first region of a substrate, and a non-volatile memory (NVM) cell including a select gate and a memory gate formed in a first recess in a second region of the same substrate, wherein the recess is recessed relative to a first surface of the substrate. The metal-gate logic transistor includes a planarized surface above and substantially parallel to the first surface, and top surfaces of the select gate and memory gate are approximately at or below an elevation of the planarized surface of the metal-gate. Generally, at least one of the top surfaces of the select gate or the memory gate includes a silicide formed thereon. Other embodiments are also disclosed.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: December 3, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Sung-Taeg Kang, James Pak, Unsoon Kim, Inkuk Kang, Chun Chen, Kuo-Tung Chang
  • Patent number: 10242996
    Abstract: A semiconductor device and method of fabricating the same are disclosed. The method includes depositing a polysilicon gate layer over a gate dielectric formed over a surface of a substrate in a peripheral region, forming a dielectric layer over the polysilicon gate layer and depositing a height-enhancing (HE) film over the dielectric layer. The HE film, the dielectric layer, the polysilicon gate layer and the gate dielectric are then patterned for a high-voltage Field Effect Transistor (HVFET) gate to be formed in the peripheral region. A high energy implant is performed to form at least one lightly doped region in a source or drain region in the substrate adjacent to the HVFET gate. The HE film is then removed, and a low voltage (LV) logic FET formed on the substrate in the peripheral region. In one embodiment, the LV logic FET is a high-k metal-gate logic FET.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: March 26, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Chun Chen, James Pak, Unsoon Kim, Inkuk Kang, Sung-Taeg Kang, Kuo Tung Chang
  • Publication number: 20190027484
    Abstract: Systems and methods of forming such include method, forming a memory gate (MG) stack in a first region, forming a sacrificial polysilicon gate on a high-k dielectric in a second region, wherein the first and second regions are disposed in a single substrate. Then a select gate (SG) may be formed adjacent to the MG stack in the first region of the semiconductor substrate. The sacrificial polysilicon gate may be replaced with a metal gate to form a logic field effect transistor (FET) in the second region. The surfaces of the substrate in the first region and the second region are substantially co-planar.
    Type: Application
    Filed: December 20, 2017
    Publication date: January 24, 2019
    Applicant: Cypress Semiconductor Corporation
    Inventors: Chun Chen, James Pak, Unsoon Kim, Inkuk Kang, Sung-Taeg Kang, Kuo Tung Chang
  • Publication number: 20190027487
    Abstract: A semiconductor device and method of fabricating the same are disclosed. The method includes depositing a polysilicon gate layer over a gate dielectric formed over a surface of a substrate in a peripheral region, forming a dielectric layer over the polysilicon gate layer and depositing a height-enhancing (HE) film over the dielectric layer. The HE film, the dielectric layer, the polysilicon gate layer and the gate dielectric are then patterned for a high-voltage Field Effect Transistor (HVFET) gate to be formed in the peripheral region. A high energy implant is performed to form at least one lightly doped region in a source or drain region in the substrate adjacent to the HVFET gate. The HE film is then removed, and a low voltage (LV) logic FET formed on the substrate in the peripheral region. In one embodiment, the LV logic FET is a high-k metal-gate logic FET.
    Type: Application
    Filed: December 20, 2017
    Publication date: January 24, 2019
    Applicant: Cypress Semiconductor Corporation
    Inventors: Chun Chen, James Pak, Unsoon Kim, Inkuk Kang, Sung-Taeg Kang, Kuo Tung Chang
  • Patent number: 10153349
    Abstract: A method of forming a split gate memory cell structure using a substrate includes forming a gate stack comprising a select gate and a dielectric portion overlying the select gate. A charge storage layer is formed over the substrate including over the gate stack. A first sidewall spacer of conductive material is formed along a first sidewall of the gate stack extending past a top of the select gate. A second sidewall spacer of dielectric material is formed along the first sidewall on the first sidewall spacer. A portion of the first sidewall spacer is silicided using the second sidewall spacer as a mask whereby silicide does not extend to the charge storage layer.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: December 11, 2018
    Assignee: NXP USA, Inc.
    Inventors: Cheong Min Hong, Sung-Taeg Kang
  • Publication number: 20180166458
    Abstract: A semiconductor device and method of making the same are disclosed. The semiconductor device includes a metal-gate logic transistor formed in a first region of a substrate, and a non-volatile memory (NVM) cell including a select gate and a memory gate formed in a first recess in a second region of the same substrate, wherein the recess is recessed relative to a first surface of the substrate. The metal-gate logic transistor includes a planarized surface above and substantially parallel to the first surface, and top surfaces of the select gate and memory gate are approximately at or below an elevation of the planarized surface of the metal-gate. Generally, at least one of the top surfaces of the select gate or the memory gate includes a silicide formed thereon. Other embodiments are also disclosed.
    Type: Application
    Filed: October 12, 2017
    Publication date: June 14, 2018
    Applicant: Cypress Semiconductor Corporation
    Inventors: Sung-Taeg Kang, James Pak, Unsoon KIM, Inkuk Kang, Chun Chen, Kuo-Tung Chang
  • Patent number: 9853039
    Abstract: A semiconductor device including a non-volatile memory (NVM) cell and method of making the same are disclosed. The semiconductor device includes a metal-gate logic transistor formed on a logic region of a substrate, and the NVM cell integrally formed in a first recess in a memory region of the same substrate, wherein the first recess is recessed relative to a first surface of the substrate in the logic region. Generally, the metal-gate logic transistor further including a planarized surface above and substantially parallel to the first surface of the substrate in the logic region, and the NVM cell is arranged below an elevation of the planarized surface of the metal-gate. In some embodiments, logic transistor is a High-k Metal-gate (HKMG) logic transistor with a gate structure including a metal-gate and a high-k gate dielectric. Other embodiments are also disclosed.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: December 26, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: Sung-Taeg Kang, James Pak, Unsoon Kim, Inkuk Kang, Chun Chen, Kuo-Tung Chang
  • Patent number: 9818755
    Abstract: A semiconductor device including a non-volatile memory (NVM) cell and method of making the same are disclosed. The semiconductor device includes a metal-gate logic transistor formed on a logic region of a substrate, and the NVM cell integrally formed in a first recess in a memory region of the same substrate, wherein the first recess is recessed relative to a first surface of the substrate in the logic region. Generally, the metal-gate logic transistor further including a planarized surface above and substantially parallel to the first surface of the substrate in the logic region, and the NVM cell is arranged below an elevation of the planarized surface of the metal-gate. In some embodiments, logic transistor is a High-k Metal-gate (HKMG) logic transistor with a gate structure including a metal-gate and a high-k gate dielectric. Other embodiments are also disclosed.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: November 14, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: Sung-Taeg Kang, James Pak, Unsoon Kim, Inkuk Kang, Chun Chen, Kuo-Tung Chang
  • Publication number: 20170194444
    Abstract: A method of forming a split gate memory cell structure using a substrate includes forming a gate stack comprising a select gate and a dielectric portion overlying the select gate. A charge storage layer is formed over the substrate including over the gate stack. A first sidewall spacer of conductive material is formed along a first sidewall of the gate stack extending past a top of the select gate. A second sidewall spacer of dielectric material is formed along the first sidewall on the first sidewall spacer. A portion of the first sidewall spacer is silicided using the second sidewall spacer as a mask whereby silicide does not extend to the charge storage layer.
    Type: Application
    Filed: January 24, 2017
    Publication date: July 6, 2017
    Inventors: CHEONG MIN HONG, SUNG-TAEG KANG
  • Patent number: 9685339
    Abstract: A split gate memory array includes a first row having memory cells; a second row having memory cells, wherein the second row is adjacent to the first row; and a plurality of segments. Each segment includes a first plurality of memory cells of the first row, a second plurality of memory cells of the second row, a first control gate portion which forms a control gate of each memory cell of the first plurality of memory cells, and a second control gate portion which forms a control gate of each memory cell of the second plurality of memory cells. The first control gate portion and the second control gate portion converge to a single control gate portion between neighboring segments of the plurality of segments.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: June 20, 2017
    Assignee: NXP USA, Inc.
    Inventors: Jane A. Yater, Cheong Min Hong, Sung-Taeg Kang, Ronald J. Syzdek
  • Patent number: 9590058
    Abstract: A method of forming a split gate memory cell structure using a substrate includes forming a gate stack comprising a select gate and a dielectric portion overlying the select gate. A charge storage layer is formed over the substrate including over the gate stack. A first sidewall spacer of conductive material is formed along a first sidewall of the gate stack extending past a top of the select gate. A second sidewall spacer of dielectric material is formed along the first sidewall on the first sidewall spacer. A portion of the first sidewall spacer is silicided using the second sidewall spacer as a mask whereby silicide does not extend to the charge storage layer.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: March 7, 2017
    Assignee: NXP USA, INC.
    Inventors: Cheong Min Hong, Sung-Taeg Kang
  • Patent number: 9397201
    Abstract: A method of forming a flash memory cell includes forming a first hard mask and a second hard mask on a substrate. A select gate is formed as a spacer around the first hard mask. A charge storage layer is formed over the first and second hard masks and the select gate. A control gate is formed as a spacer around the second hard mask. A recess in the control gate is filled with a dielectric material. The recess is formed between a curved sidewall of the control gate and a sidewall of the charge storage layer directly adjacent the curved sidewall of the control gate.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: July 19, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Jacob T. Williams, Cheong Min Hong, Sung-Taeg Kang, David G. Kolar, Jane A. Yater
  • Patent number: 9368499
    Abstract: A method and apparatus are described for integrating high voltage (HV) transistor devices and medium voltage or dual gate oxide (DGO) transistor devices with low voltage (LV) core transistor devices on a single substrate, where each high voltage transistor device (160) includes a metal gate (124), an upper high-k gate dielectric layer (120), a middle gate dielectric layer (114) formed with a relatively lower high-k dual gate oxide layer, and a lower high voltage gate dielectric stack (108, 110) formed with one or more low-k gate oxide layers (22), where each DGO transistor device (161) includes a metal gate (124), an upper high-k gate dielectric layer (120), and a middle gate dielectric layer (114) formed with a relatively lower high-k dual gate oxide layer, and where each core transistor device (162) includes a metal gate (124), an upper high-k gate dielectric layer (120), and a base oxide layer (118) formed with one or more low-k gate oxide layers.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: June 14, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Cheong Min Hong, Asanga H. Perera, Sung-Taeg Kang
  • Patent number: 9356106
    Abstract: Methods for fabricating dense arrays of electrically conductive nanocrystals that are self-aligned in depressions at target locations on a substrate, and semiconductor devices configured with nanocrystals situated within a gate stack as a charge storage area for a nonvolatile memory (NVM) device, are provided.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: May 31, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Euhngi Lee, Sung-Taeg Kang
  • Publication number: 20160126327
    Abstract: A method includes forming a first dielectric layer over a memory region and a second dielectric layer over a logic region. A first polysilicon layer is formed over the first and second dielectric layers. An opening is formed in the first polysilicon layer in the memory region. A charge storage layer is formed over the first polysilicon layer and in the opening. A second polysilicon layer is formed over the charge storage layer including in the opening. The second polysilicon layer is etched to remove the second polysilicon layer from over the first polysilicon layer and to leave a portion of the second polysilicon layer in the opening. The first polysilicon layer is etched to form a first gate in the logic region and the second polysilicon layer is etched in the opening to define a control gate of a first NVM cell and a control gate of a second NVM cell.
    Type: Application
    Filed: October 29, 2014
    Publication date: May 5, 2016
    Inventors: WEIZE CHEN, SUNG-TAEG KANG, PATRICE M. PARRIS
  • Patent number: 9331092
    Abstract: Methods and related structures are disclosed for forming contact landing regions in split-gate NVM (non-volatile memory) systems. A dummy select gate structure is formed while also forming select gates for split-gate NVM cells. A control gate layer is formed over the select gates and the dummy select gate structure, as well as an intervening charge storage layer. The control gate material will fill in gaps between the select gate material and the dummy select gate material. A non-patterned spacer etch is then used to etch the control gate layer to form a contact landing region associated with the dummy select gate structure while also forming spacer control gates for the split-gate NVM cells. The disclosed embodiments provide improved (e.g., more planar) contact landing regions without requiring additional processing steps and without increasing the pitch of the resulting NVM cell array.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: May 3, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Jane A. Yater, Cheong Min Hong, Sung-Taeg Kang
  • Patent number: 9318568
    Abstract: A method of making a semiconductor device includes forming a memory gate structure in a nonvolatile memory region of the semiconductor device, wherein the memory gate structure comprises a first gate separated from a second gate by a charge storage layer. A logic gate structure is formed in a logic region of the semiconductor device. A hard mask is formed over at least the metal electrode portion. The nonvolatile memory region is selectively etched such that a first recess is formed in the first gate and a second recess is formed in the second gate.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: April 19, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Asanga H. Perera, Sung-Taeg Kang
  • Publication number: 20160087058
    Abstract: A method of making a semiconductor device includes forming a memory gate structure in a nonvolatile memory region of the semiconductor device, wherein the memory gate structure comprises a first gate separated from a second gate by a charge storage layer. A logic gate structure is formed in a logic region of the semiconductor device. A hard mask is formed over at least the metal electrode portion. The nonvolatile memory region is selectively etched such that a first recess is formed in the first gate and a second recess is formed in the second gate.
    Type: Application
    Filed: September 19, 2014
    Publication date: March 24, 2016
    Inventors: ASANGA H. PERERA, Sung-Taeg Kang
  • Publication number: 20160071943
    Abstract: Methods for fabricating dense arrays of electrically conductive nanocrystals that are self-aligned in depressions at target locations on a substrate, and semiconductor devices configured with nanocrystals situated within a gate stack as a charge storage area for a nonvolatile memory (NVM) device, are provided.
    Type: Application
    Filed: September 4, 2014
    Publication date: March 10, 2016
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Euhngi Lee, Sung-Taeg Kang