Patents by Inventor Sung-Won Yun
Sung-Won Yun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240100572Abstract: The inventive concept provides a substrate treating apparatus. The substrate treating apparatus includes a support unit configured to support a substrate; and a cleaning unit configured to clean a bottom surface of the substrate supported on the support unit, and wherein the cleaning unit comprises: a body; and a protrusion formed to be upwardly protruding from the body, and the protrusion is positioned to be spaced apart from the bottom surface.Type: ApplicationFiled: March 13, 2023Publication date: March 28, 2024Applicant: SEMES CO., LTD.Inventors: Sung Hun EOM, Tae Won Yun, Ha Neul Yoo, Ji Hyeong Yu
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Publication number: 20230410900Abstract: A memory device including a first substrate, a peripheral circuit provided on the first substrate, a first metal bonding layer provided on the peripheral circuit, a second metal bonding layer directly bonded to the first metal bonding layer, a memory cell array provided on the second metal bonding layer; and a second substrate provided on the memory cell array. A page buffer circuit in the peripheral circuit receives a verification result through the metal bonding layers, divides the verification result into stages, and sequentially outputs the verification result for the division into the stages, and a pass/failure checker in the peripheral circuit sequentially performs a counting operation about each of the stages to generate accumulated values, and compares the accumulated values and a reference value which increases from an initial value as the counting operation is performed, and the initial value is set by an external memory controller.Type: ApplicationFiled: August 25, 2023Publication date: December 21, 2023Inventors: Hyejin YIM, Sung-Won YUN, Il Han PARK
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Patent number: 11776642Abstract: A method of operating a memory device that includes a plurality of stages each having a plurality of page buffers. The method including performing a verify operation of a first program loop from among a plurality of program loops, the verify operation of the first program loop including, performing a first off-cell counting operation on a first stage of the plurality of stages based on a first sampling rate to generate a first off-cell counting result; selectively changing the first sampling rate based on the first off-cell counting result to generate a changed first sampling rate; and performing a second off-cell counting operation on a second stage of the plurality of stages based on one of the first sampling rate and the changed first sampling rate to generate a second off-cell counting result.Type: GrantFiled: December 13, 2021Date of Patent: October 3, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Won Yun, Han-Jun Lee
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Patent number: 11756613Abstract: A memory device includes: a first substrate; a peripheral circuit provided on the first substrate; a first metal bonding layer provided on the peripheral circuit; a second metal bonding layer directly bonded to the first metal bonding layer; a memory cell array provided on the second metal bonding layer; and a second substrate provided on the memory cell array. A page buffer circuit in the peripheral circuit receives a verification result through the metal bonding layers, divides the verification result into stages, and sequentially outputs the verification result for the division into the stages, and a pass/failure checker in the peripheral circuit sequentially performs a counting operation about each of the stages to generate accumulated values, and compares the accumulated values and a reference value which increases from an initial value as the counting operation is performed, and the initial value is set by an external memory controller.Type: GrantFiled: September 1, 2022Date of Patent: September 12, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Hyejin Yim, Sung-Won Yun, Il Han Park
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Patent number: 11594294Abstract: A method of operating a memory device that includes a plurality of stages each having a plurality of page buffers. The method including performing a verify operation of a first program loop from among a plurality of program loops, the verify operation of the first program loop including, performing a first off-cell counting operation on a first stage of the plurality of stages based on a first sampling rate to generate a first off-cell counting result; selectively changing the first sampling rate based on the first off-cell counting result to generate a changed first sampling rate; and performing a second off-cell counting operation on a second stage of the plurality of stages based on one of the first sampling rate and the changed first sampling rate to generate a second off-cell counting result.Type: GrantFiled: October 4, 2021Date of Patent: February 28, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-won Yun, Han-jun Lee
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Publication number: 20220415388Abstract: A memory device includes: a first substrate; a peripheral circuit provided on the first substrate; a first metal bonding layer provided on the peripheral circuit; a second metal bonding layer directly bonded to the first metal bonding layer; a memory cell array provided on the second metal bonding layer; and a second substrate provided on the memory cell array. A page buffer circuit in the peripheral circuit receives a verification result through the metal bonding layers, divides the verification result into stages, and sequentially outputs the verification result for the division into the stages, and a pass/failure checker in the peripheral circuit sequentially performs a counting operation about each of the stages to generate accumulated values, and compares the accumulated values and a reference value which increases from an initial value as the counting operation is performed, and the initial value is set by an external memory controller.Type: ApplicationFiled: September 1, 2022Publication date: December 29, 2022Inventors: Hyejin YIM, Sung-Won YUN, Il Han PARK
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Patent number: 11437094Abstract: A memory device includes: a first substrate; a peripheral circuit provided on the first substrate; a first metal bonding layer provided on the peripheral circuit; a second metal bonding layer directly bonded to the first metal bonding layer; a memory cell array provided on the second metal bonding layer; and a second substrate provided on the memory cell array. A page buffer circuit in the peripheral circuit receives a verification result through the metal bonding layers, divides the verification result into stages, and sequentially outputs the verification result for the division into the stages, and a pass/failure checker in the peripheral circuit sequentially performs a counting operation about each of the stages to generate accumulated values, and compares the accumulated values and a reference value which increases from an initial value as the counting operation is performed, and the initial value is set by an external memory controller.Type: GrantFiled: September 11, 2020Date of Patent: September 6, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Hyejin Yim, Sung-Won Yun, Il Han Park
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Publication number: 20220101931Abstract: A method of operating a memory device that includes a plurality of stages each having a plurality of page buffers. The method including performing a verify operation of a first program loop from among a plurality of program loops, the verify operation of the first program loop including, performing a first off-cell counting operation on a first stage of the plurality of stages based on a first sampling rate to generate a first off-cell counting result; selectively changing the first sampling rate based on the first off-cell counting result to generate a changed first sampling rate; and performing a second off-cell counting operation on a second stage of the plurality of stages based on one of the first sampling rate and the changed first sampling rate to generate a second off-cell counting result.Type: ApplicationFiled: December 13, 2021Publication date: March 31, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Sung-won YUN, Han-jun LEE
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Publication number: 20220028464Abstract: A method of operating a memory device that includes a plurality of stages each having a plurality of page buffers. The method including performing a verify operation of a first program loop from among a plurality of program loops, the verify operation of the first program loop including, performing a first off-cell counting operation on a first stage of the plurality of stages based on a first sampling rate to generate a first off-cell counting result; selectively changing the first sampling rate based on the first off-cell counting result to generate a changed first sampling rate; and performing a second off-cell counting operation on a second stage of the plurality of stages based on one of the first sampling rate and the changed first sampling rate to generate a second off-cell counting result.Type: ApplicationFiled: October 4, 2021Publication date: January 27, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Sung-won YUN, Han-jun LEE
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Patent number: 11164646Abstract: A method of operating a memory device that includes a plurality of stages each having a plurality of page buffers. The method including performing a verify operation of a first program loop from among a plurality of program loops, the verify operation of the first program loop including, performing a first off-cell counting operation on a first stage of the plurality of stages based on a first sampling rate to generate a first off-cell counting result; selectively changing the first sampling rate based on the first off-cell counting result to generate a changed first sampling rate; and performing a second off-cell counting operation on a second stage of the plurality of stages based on one of the first sampling rate and the changed first sampling rate to generate a second off-cell counting result.Type: GrantFiled: March 2, 2020Date of Patent: November 2, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-won Yun, Han-jun Lee
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Publication number: 20200411086Abstract: A memory device includes: a first substrate; a peripheral circuit provided on the first substrate; a first metal bonding layer provided on the peripheral circuit; a second metal bonding layer directly bonded to the first metal bonding layer; a memory cell array provided on the second metal bonding layer; and a second substrate provided on the memory cell array. A page buffer circuit in the peripheral circuit receives a verification result through the metal bonding layers, divides the verification result into stages, and sequentially outputs the verification result for the division into the stages, and a pass/failure checker in the peripheral circuit sequentially performs a counting operation about each of the stages to generate accumulated values, and compares the accumulated values and a reference value which increases from an initial value as the counting operation is performed, and the initial value is set by an external memory controller.Type: ApplicationFiled: September 11, 2020Publication date: December 31, 2020Inventors: Hyejin YIM, Sung-Won YUN, Il Han PARK
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Patent number: 10826399Abstract: A method includes generating a gain transition signal in response to any one of an average value of a feedback signal, a slope of the feedback signal, a slope of an input signal of the power converter, a maximum value of the input signal, and a minimum value of the input signal, and generating a first gain control signal and a second gain control signal in response to the gain transition signal. A gain transition controller includes a transition signal generator generating the gain transition signal and a gain control signal generator generating the first gain control signal and the second gain control signal in response to the gain transition signal.Type: GrantFiled: April 23, 2019Date of Patent: November 3, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Hyun-Chul Eum, Tae-Sung Kim, Young-Mo Yang, Sung-Won Yun, Woo-Kang Jin
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Patent number: 10777264Abstract: A program verification method for a nonvolatile memory device includes performing a first failure bit counting operation about a first stage to generate a first failure bit accumulated value and comparing the first failure bit accumulated value and a first failure reference value to determine a program failure. When the first failure bit accumulated value is less than the first failure reference value, a second failure bit counting operation for a second stage is performed to generate a second failure bit accumulated value. The second failure bit accumulated value is compared to a second reference value to determine a program failure. The second failure reference value is different from the first failure reference value.Type: GrantFiled: August 22, 2018Date of Patent: September 15, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Hyejin Yim, Sung-Won Yun, Il Han Park
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Patent number: 10748632Abstract: A nonvolatile memory device includes multiple memory cells including first memory cells and second memory cells. A method of programming the nonvolatile memory device includes: performing first programming to apply a programming forcing voltage to a bit line of each of the first memory cells; and dividing the second memory cells into a first cell group, a second cell group, and a third cell group, based on a threshold voltage of the second memory cells after performing the first programming. The method also includes performing second programming to apply a programming inhibition voltage to the bit line of each of the first memory cells and a bit line of each of memory cells of the first cell group. A level of the programming forcing voltage is lower than that of the programming inhibition voltage.Type: GrantFiled: November 21, 2018Date of Patent: August 18, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Won Yun, Hye-Jin Yim
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Publication number: 20200202960Abstract: A method of operating a memory device that includes a plurality of stages each having a plurality of page buffers. The method including performing a verify operation of a first program loop from among a plurality of program loops, the verify operation of the first program loop including, performing a first off-cell counting operation on a first stage of the plurality of stages based on a first sampling rate to generate a first off-cell counting result; selectively changing the first sampling rate based on the first off-cell counting result to generate a changed first sampling rate; and performing a second off-cell counting operation on a second stage of the plurality of stages based on one of the first sampling rate and the changed first sampling rate to generate a second off-cell counting result.Type: ApplicationFiled: March 2, 2020Publication date: June 25, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Sung-won YUN, Han-jun LEE
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Patent number: 10629279Abstract: A method of operating a memory device that includes a plurality of stages each having a plurality of page buffers. The method including performing a verify operation of a first program loop from among a plurality of program loops, the verify operation of the first program loop including, performing a first off-cell counting operation on a first stage of the plurality of stages based on a first sampling rate to generate a first off-cell counting result; selectively changing the first sampling rate based on the first off-cell counting result to generate a changed first sampling rate; and performing a second off-cell counting operation on a second stage of the plurality of stages based on one of the first sampling rate and the changed first sampling rate to generate a second off-cell counting result.Type: GrantFiled: June 15, 2018Date of Patent: April 21, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-won Yun, Han-jun Lee
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Publication number: 20190252984Abstract: A method includes generating a gain transition signal in response to any one of an average value of a feedback signal, a slope of the feedback signal, a slope of an input signal of the power converter, a maximum value of the input signal, and a minimum value of the input signal, and generating a first gain control signal and a second gain control signal in response to the gain transition signal. A gain transition controller includes a transition signal generator generating the gain transition signal and a gain control signal generator generating the first gain control signal and the second gain control signal in response to the gain transition signal.Type: ApplicationFiled: April 23, 2019Publication date: August 15, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Hyun-Chul EUM, Tae-Sung KIM, Young-Mo YANG, Sung-Won YUN, Woo-Kang JIN
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Publication number: 20190164618Abstract: A nonvolatile memory device includes multiple memory cells including first memory cells and second memory cells. A method of programming the nonvolatile memory device includes: performing first programming to apply a programming forcing voltage to a bit line of each of the first memory cells; and dividing the second memory cells into a first cell group, a second cell group, and a third cell group, based on a threshold voltage of the second memory cells after performing the first programming. The method also includes performing second programming to apply a programming inhibition voltage to the bit line of each of the first memory cells and a bit line of each of memory cells of the first cell group. A level of the programming forcing voltage is lower than that of the programming inhibition voltage.Type: ApplicationFiled: November 21, 2018Publication date: May 30, 2019Inventors: SUNG-WON YUN, HYE-JIN YIM
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Publication number: 20190147964Abstract: A method of operating a memory device that includes a plurality of stages each having a plurality of page buffers. The method including performing a verify operation of a first program loop from among a plurality of program loops, the verify operation of the first program loop including, performing a first off-cell counting operation on a first stage of the plurality of stages based on a first sampling rate to generate a first off-cell counting result; selectively changing the first sampling rate based on the first off-cell counting result to generate a changed first sampling rate; and performing a second off-cell counting operation on a second stage of the plurality of stages based on one of the first sampling rate and the changed first sampling rate to generate a second off-cell counting result.Type: ApplicationFiled: June 15, 2018Publication date: May 16, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Sung-won Yun, Han-jun Lee
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Patent number: 10291130Abstract: A method includes generating a first gain control signal and a second gain control signal in response to a gain transition signal indicating a transition of a power converter from a first gain mode to a second gain mode. The method further includes causing the power converter to enter the first gain mode in response to the first gain control signal, and causing the power converter to enter the second gain mode in response to the second gain control signal. A circuit includes a gain transition controller generating a first gain control signal and a second gain control signal in response to a gain transition signal, and a gain control circuit causing the power converter to enter the first gain mode in response to the first gain control signal and causing the power converter to enter the second gain mode in response to the second gain control signal.Type: GrantFiled: May 24, 2017Date of Patent: May 14, 2019Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Hyun-Chul Eum, Tae-Sung Kim, Young-Mo Yang, Sung-Won Yun, Woo-Kang Jin