Abstract: A hybrid beamforming device utilizes analog beamformers (ABF) and digital beamformers (DBF) to produce a desired radio frequency radiation pattern having one or more lobes pointing in particular directions. A set of directions, such as each pointing toward a different candidate area of the sky, are processed to determine a coarse direction. ABF beam coefficients are determined based on the coarse direction. DBF beam coefficients are determined based on the directions in the set of directions, providing more precise directionality in the pattern. The ABF beam coefficients may be sent to the ABFs at a first cadence, such as every second. The DBF beam coefficients may be sent to the DBFs at a second cadence that is faster than the first cadence, such as every millisecond. This facilitates rapid scanning of different precision directions, such as of different portions of the sky to receive a broadcast transmission from a satellite.

Abstract: A method and a communication device for enabling execution of a virtual activity in a physical environment, wherein development of the virtual activity is presented to a user via at least one user interface of a communication device, the method including: determining a trajectory of the communication device; capturing and consolidating sensor data associated with the physical environment and virtual data associated with the virtual activity; generating at least two mutually dependent zones in the physical environment based on the captured and consolidated data and the trajectory of the communication device, and presenting an updated scene of the virtual activity, including at least parts of the zones via at least one of the user interfaces of the communication device.

Abstract: A Successive Approximation Register, SAR, Analog to Digital Converter, ADC, (50) achieves high speed and accuracy by (1) alternating at least some decisions between sets of comparators having different accuracy and noise characteristics, and (2) unevenly allocating redundancy (in the form of LSBs of range) for successive decisions according to the accuracy/noise of the comparator used for the preceding decision. The redundancy allocation is compensated by the addition of decision cycles. Alternating between different comparators removes the comparator reset time (treset) from the critical path, at least for those decision cycles. The uneven allocation of redundancy—specifically, allocating more redundancy to decision cycles immediately following the use of a lower accuracy/higher noise comparators—compensates for the lower accuracy and prevents the need for larger redundancy (relative to the full-scale range of a decision cycle) later in the ADC process.

Abstract: A SAR ADC (50) is disclosed. It comprises a differential input port having a first input (VinP) configured to receive a first input voltage and a second input (VinN) configured to receive a second input voltage, of opposite polarity compared with first input voltage. Furthermore, it comprises a (300) having a first sub circuit (310P) comprising a first plurality of capacitors (2Cu, Cu), each connected to a common node (320P) of the first sub circuit (310P) with a first terminal, and a second sub circuit (310N) comprising a second plurality of capacitors (2Cu, Cu), each connected to a common node (320N) of the second sub circuit (310N) with a first terminal.

Abstract: Technologies directed to using selective true-time delay for energy efficient beam squint mitigation in phased array antennas in communication systems are described. One communication system includes a first register to store a first value indicative of a mode of operation of the communication system and a second register to store a value corresponding to a first time duration. The communication system includes antenna elements, digital beamforming (DBF) devices, phase shifters, and delay circuitry. In a first mode, the delay circuitry does not delay a first signal and, in a second mode, the delay circuitry delays a second signal.

Abstract: Technologies directed to correction of terrestrial interference using hybrid beamforming are described. One method includes a first communication device with beamforming circuitry receiving an indication of a first direction towards a second communication device The method further includes determining that orienting a main lobe of an antenna gain pattern of the beamforming circuitry along the first direction results in RF saturation of the beamforming circuitry using first data that indicates a set of directions comprising the first direction and a status of an RF saturation condition corresponding to each of the set of directions. The method further includes using the first data to determine a second direction that is different from the first direction. Orienting the main lobe along the second direction does not result in RF saturation. The method further includes receiving, a first RF signal at a first time with the main lobe oriented in the second direction.

Abstract: Technologies directed to binning methods for electronically steered transmit phased arrays with amplitude tapering are described. One communication system includes a first and a second set of power amplifiers. The first set operates with a first peak power level and the second set operates with a second peak power level that is lower than the first peak power level. A digital beamforming (DBF) device sends a first set of signals to the first set of power amplifiers causing the first set of power amplifiers to operate in a first range. The DBF also sends a second set of signals to the second set of power amplifiers causing the second set of power amplifiers to operate in a second range.

Abstract: Technologies directed to a receiver circuit with selective time-interleaved analog-to-digital converters (ADCs) are described. The receiver circuit includes a first ADC, a second ADC, and a digital processing circuit coupled to the first ADC and second ADC that operates in a first mode or a second mode. In the first mode the first ADC receives a first signal and generates first samples at a first sampling frequency. The digital processing circuit processes the first samples. In the second mode, the first ADC and the second ADC both receive a second signal and collectively generate second samples at a second sampling frequency that is greater than the first sampling frequency. The digital processing circuit processes the second samples.

Abstract: A Successive Approximation Register, SAR, Analog to Digital Converter, ADC, (50) achieves high speed and accuracy by (1) alternating at least some decisions between sets of comparators having different accuracy and noise characteristics, and (2) unevenly allocating redundancy (in the form of LSBs of range) for successive decisions according to the accuracy/noise of the comparator used for the preceding decision. The redundancy allocation is compensated by the addition of decision cycles. Alternating between different comparators removes the comparator reset time (treset) from the critical path, at least for those decision cycles. The uneven allocation of redundancy—specifically, allocating more redundancy to decision cycles immediately following the use of a lower accuracy/higher noise comparators—compensates for the lower accuracy and prevents the need for larger redundancy (relative to the full-scale range of a decision cycle) later in the ADC process.

Abstract: A multipath bootstrapped sampling circuit includes a sampling capacitor, a sampling transistor interposed between the sampling capacitor and the analog input signal voltage, two bootstrap capacitors, and a bootstrap switching network periodically transitioning between a holding phase and a tracking phase. The bootstrap switching network includes a primary bootstrap path that drives only one load: the gate terminal of the sampling transistor. One or more auxiliary bootstrap paths drive other transistors in the bootstrap switching network. This absolutely minimizes the parasitic capacitance due to fan-out on the primary bootstrap path. Additionally, the provision of two (or more) bootstrap capacitors allows bulk terminals of transistors on the primary bootstrap path to be connected to an auxiliary bootstrap path, further reducing parasitic capacitance on the primary bootstrap path.

Abstract: An analog-to-digital converter (ADC) is provided, having two comparators, two digital-to-analog converters (DACs), and an adder circuit. The ADC receives an input value and, over a plurality of conversion cycles of the ADC, generates an output value representative of the input value. Each respective DAC generates a plurality of threshold levels, which are defined, at least in part, by predetermined redundancy levels that are binary-scaled. The comparator arrangement provides an output code in a respective conversion cycle and, for at least two adjacent conversion cycles, the two comparators collectively provide 2-bit output codes. The adder circuit provides a plurality of output bits of the output value, and is capable of overlapping and adding a first significant bit of the 2-bit output code provided for a predetermined conversion cycle with a second significant bit of the 2-bit output code provided for a previous conversion cycle to generate one output bit.

Abstract: An analog-to-digital converter (ADC) is provided, having two comparators, two digital-to-analog converters (DACs), and an adder circuit. The ADC receives an input value and, over a plurality of conversion cycles of the ADC, generates an output value representative of the input value. Each respective DAC generates a plurality of threshold levels, which are defined, at least in part, by predetermined redundancy levels that are binary-scaled. The comparator arrangement provides an output code in a respective conversion cycle and, for at least two adjacent conversion cycles, the two comparators collectively provide 2-bit output codes. The adder circuit provides a plurality of output bits of the output value, and is capable of overlapping and adding a first significant bit of the 2-bit output code provided for a predetermined conversion cycle with a second significant bit of the 2-bit output code provided for a previous conversion cycle to generate one output bit.

Abstract: Representative implementations of devices and techniques provide analog to digital conversion of time-discrete analog inputs. A redundant binary scaled capacitance arrangement using a successive approximation technique can provide a fast and power efficient ADC, with improved error correction. For example, a successive approximation capacitor arrangement may include multiple arrays of capacitances with binary bit weights. In an implementation, the technique includes processing the capacitances in successive cycles, where each cycle generates a binary error correction code representing greater than one bit of the digital output.