Patents by Inventor Suresh Belani
Suresh Belani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10229893Abstract: A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing time.Type: GrantFiled: March 13, 2017Date of Patent: March 12, 2019Assignee: VISHAY-SILICONIXInventors: Frank Kuo, Suresh Belani
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Publication number: 20170271304Abstract: A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing time.Type: ApplicationFiled: March 13, 2017Publication date: September 21, 2017Inventors: Frank Kuo, Suresh Belani
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Patent number: 9595503Abstract: A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing time.Type: GrantFiled: September 2, 2014Date of Patent: March 14, 2017Assignee: VISHAY-SILICONIXInventors: Frank Kuo, Suresh Belani
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Patent number: 9379045Abstract: A first embodiment is a common drain+clip 20. It has a conventional drain contact on its bottom surface and is flip chip mounted on a half-etched leadframe 40 which has external source, gate and drain contacts connected to the sources, gate and common drain of the die 20. Common drain clip 50 connects the drain 30 to external contacts between opposite gate contacts. A second embodiment is a direct drain embodiment+heatslug. The device 80 has a top drain contact 36 that extends to the common drain 30 across the bottom of the die which is flip chip mounted to a half-etched leadframe having external source, gate and drain contacts connected to the sources, gates and common drain of the die 80.Type: GrantFiled: September 13, 2013Date of Patent: June 28, 2016Assignee: Fairchild Semiconductor CorporationInventors: Chung-Lin Wu, Steven Sapp, Bigildis Dosdos, Suresh Belani, Sunggeun Yoon
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Patent number: 9184152Abstract: A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing time.Type: GrantFiled: July 26, 2014Date of Patent: November 10, 2015Assignee: Vishay-SiliconixInventors: Frank Kuo, Suresh Belani
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Publication number: 20140370661Abstract: A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing time.Type: ApplicationFiled: September 2, 2014Publication date: December 18, 2014Applicant: SILICONIX ELECTRONIC CO., LTD.Inventors: Frank Kuo, Suresh Belani
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Publication number: 20140332939Abstract: A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing dine.Type: ApplicationFiled: July 26, 2014Publication date: November 13, 2014Applicant: Siliconix Electronic Co., LTD.Inventors: Frank Kuo, Suresh Belani
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Patent number: 8822273Abstract: A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing time.Type: GrantFiled: September 9, 2011Date of Patent: September 2, 2014Assignee: Vishay-SiliconixInventors: Frank Kuo, Suresh Belani
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Patent number: 8723300Abstract: The multi-chip leadless module 200 has integrated circuit (IC) 150, dual n-channel mosfet 110, IC leads 210, 211, 212, gate leads 213, 213, and source leads 217-220 encapsulated in resin 250. The IC 150 and the dual n-channel mosfet 110 are mounted face down on the leads. IC leads 210, 211, 212 are made of planar metal and connect, respectively, to the electrodes TEST, VDD and VM on the IC 150 using a flip chip technique to assemble the leads on copper pillars or copper studs.Type: GrantFiled: August 13, 2012Date of Patent: May 13, 2014Assignee: Fairchild Semiconductor CorporationInventors: Chung-Lin Wu, Steven Sapp, Bigildis Dosdos, Suresh Belani, Sunggeun Yoon
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Publication number: 20140070392Abstract: A first embodiment is a common drain+clip 20. It has a conventional drain contact on its bottom surface and is flip chip mounted on a half-etched leadframe 40 which has external source, gate and drain contacts connected to the sources, gate and common drain of the die 20. Common drain clip 50 connects the drain 30 to external contacts between opposite gate contacts. A second embodiment is a direct drain embodiment+heatslug. The device 80 has a top drain contact 36 that extends to the common drain 30 across the bottom of the die which is flip chip mounted to a half-etched leadframe having external source, gate and drain contacts connected to the sources, gates and common drain of the die 80.Type: ApplicationFiled: September 13, 2013Publication date: March 13, 2014Applicant: Fairchild Semiconductor CorporationInventors: Chung-Lin Wu, Steven Sapp, Bigildis Dosdos, Suresh Belani, Sunggeun Yoon
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Publication number: 20140042599Abstract: The multi-chip leadless module 200 has integrated circuit (IC) 150, dual re-channel mosfet 110, IC leads 210, 211, 212, gate leads 213, 213, and source leads 217-220 encapsulated in resin 250. The IC 150 and the dual n-channel mosfet 110 are mounted face down on the leads. IC leads 210, 211, 212 are made of planar metal and connect, respectively, to the electrodes TEST, VDD and VM on the IC 150 using a flip chip technique to assemble the leads on copper pillars or copper studs.Type: ApplicationFiled: August 13, 2012Publication date: February 13, 2014Inventors: Chung-Lin Wu, Steven Sapp, Bigildis Dosdos, Suresh Belani, Sunggeun Yoon
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Patent number: 8586419Abstract: The present technology is directed toward semiconductors packaged by electrically coupling a plurality of die to an upper and lower lead frame. The opposite edges of each corresponding set of leads in the upper lead frame are bent. The leads in the upper lead frame are electrically coupled between respective contacts on respective die and respective lower portion of the leads in the lower lead frame. The bent opposite edges of each corresponding set of leads of the upper lead frame support the upper lead frame before encapsulation, for achieving a desired position of the plurality of die between the leads of the upper and lower lead frames in the packaged semiconductor. After the encapsulated die are separated, the upper leads have an L-shape and electrically couple die contacts on upper side of the die to leads on the lower side of the die so that the package contacts are on the same side of the semiconductor package.Type: GrantFiled: March 24, 2010Date of Patent: November 19, 2013Assignee: Vishay-SiliconixInventors: Serge Jaunay, Suresh Belani, Frank Kuo, Sen Mao, Peter Wang
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Publication number: 20120112331Abstract: A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing time.Type: ApplicationFiled: September 9, 2011Publication date: May 10, 2012Applicant: SILICONIX ELECTRONIC CO., LTD.Inventors: Frank Kuo, Suresh Belani
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Publication number: 20110175217Abstract: The present technology is directed toward semiconductors packaged by electrically coupling a plurality of die to an upper and lower lead frame. The opposite edges of each corresponding set of leads in the upper lead frame are bent. The leads in the upper lead frame are electrically coupled between respective contacts on respective die and respective lower portion of the leads in the lower lead frame. The bent opposite edges of each corresponding set of leads of the upper lead frame support the upper lead frame before encapsulation, for achieving a desired position of the plurality of die between the leads of the upper and lower lead frames in the packaged semiconductor. After the encapsulated die are separated, the upper leads have an L-shape and electrically couple die contacts on upper side of the die to leads on the lower side of the die so that the package contacts are on the same side of the semiconductor package.Type: ApplicationFiled: March 24, 2010Publication date: July 21, 2011Applicant: VISHAY-SILICONIXInventors: Serge Jaunay, Suresh Belani, Frank Kuo, Sen Mao, Peter Wang