Patents by Inventor Suresh Belani

Suresh Belani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10229893
    Abstract: A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing time.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: March 12, 2019
    Assignee: VISHAY-SILICONIX
    Inventors: Frank Kuo, Suresh Belani
  • Publication number: 20170271304
    Abstract: A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing time.
    Type: Application
    Filed: March 13, 2017
    Publication date: September 21, 2017
    Inventors: Frank Kuo, Suresh Belani
  • Patent number: 9595503
    Abstract: A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing time.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: March 14, 2017
    Assignee: VISHAY-SILICONIX
    Inventors: Frank Kuo, Suresh Belani
  • Patent number: 9379045
    Abstract: A first embodiment is a common drain+clip 20. It has a conventional drain contact on its bottom surface and is flip chip mounted on a half-etched leadframe 40 which has external source, gate and drain contacts connected to the sources, gate and common drain of the die 20. Common drain clip 50 connects the drain 30 to external contacts between opposite gate contacts. A second embodiment is a direct drain embodiment+heatslug. The device 80 has a top drain contact 36 that extends to the common drain 30 across the bottom of the die which is flip chip mounted to a half-etched leadframe having external source, gate and drain contacts connected to the sources, gates and common drain of the die 80.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: June 28, 2016
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Chung-Lin Wu, Steven Sapp, Bigildis Dosdos, Suresh Belani, Sunggeun Yoon
  • Patent number: 9184152
    Abstract: A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing time.
    Type: Grant
    Filed: July 26, 2014
    Date of Patent: November 10, 2015
    Assignee: Vishay-Siliconix
    Inventors: Frank Kuo, Suresh Belani
  • Publication number: 20140370661
    Abstract: A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing time.
    Type: Application
    Filed: September 2, 2014
    Publication date: December 18, 2014
    Applicant: SILICONIX ELECTRONIC CO., LTD.
    Inventors: Frank Kuo, Suresh Belani
  • Publication number: 20140332939
    Abstract: A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing dine.
    Type: Application
    Filed: July 26, 2014
    Publication date: November 13, 2014
    Applicant: Siliconix Electronic Co., LTD.
    Inventors: Frank Kuo, Suresh Belani
  • Patent number: 8822273
    Abstract: A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing time.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: September 2, 2014
    Assignee: Vishay-Siliconix
    Inventors: Frank Kuo, Suresh Belani
  • Patent number: 8723300
    Abstract: The multi-chip leadless module 200 has integrated circuit (IC) 150, dual n-channel mosfet 110, IC leads 210, 211, 212, gate leads 213, 213, and source leads 217-220 encapsulated in resin 250. The IC 150 and the dual n-channel mosfet 110 are mounted face down on the leads. IC leads 210, 211, 212 are made of planar metal and connect, respectively, to the electrodes TEST, VDD and VM on the IC 150 using a flip chip technique to assemble the leads on copper pillars or copper studs.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: May 13, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Chung-Lin Wu, Steven Sapp, Bigildis Dosdos, Suresh Belani, Sunggeun Yoon
  • Publication number: 20140070392
    Abstract: A first embodiment is a common drain+clip 20. It has a conventional drain contact on its bottom surface and is flip chip mounted on a half-etched leadframe 40 which has external source, gate and drain contacts connected to the sources, gate and common drain of the die 20. Common drain clip 50 connects the drain 30 to external contacts between opposite gate contacts. A second embodiment is a direct drain embodiment+heatslug. The device 80 has a top drain contact 36 that extends to the common drain 30 across the bottom of the die which is flip chip mounted to a half-etched leadframe having external source, gate and drain contacts connected to the sources, gates and common drain of the die 80.
    Type: Application
    Filed: September 13, 2013
    Publication date: March 13, 2014
    Applicant: Fairchild Semiconductor Corporation
    Inventors: Chung-Lin Wu, Steven Sapp, Bigildis Dosdos, Suresh Belani, Sunggeun Yoon
  • Publication number: 20140042599
    Abstract: The multi-chip leadless module 200 has integrated circuit (IC) 150, dual re-channel mosfet 110, IC leads 210, 211, 212, gate leads 213, 213, and source leads 217-220 encapsulated in resin 250. The IC 150 and the dual n-channel mosfet 110 are mounted face down on the leads. IC leads 210, 211, 212 are made of planar metal and connect, respectively, to the electrodes TEST, VDD and VM on the IC 150 using a flip chip technique to assemble the leads on copper pillars or copper studs.
    Type: Application
    Filed: August 13, 2012
    Publication date: February 13, 2014
    Inventors: Chung-Lin Wu, Steven Sapp, Bigildis Dosdos, Suresh Belani, Sunggeun Yoon
  • Patent number: 8586419
    Abstract: The present technology is directed toward semiconductors packaged by electrically coupling a plurality of die to an upper and lower lead frame. The opposite edges of each corresponding set of leads in the upper lead frame are bent. The leads in the upper lead frame are electrically coupled between respective contacts on respective die and respective lower portion of the leads in the lower lead frame. The bent opposite edges of each corresponding set of leads of the upper lead frame support the upper lead frame before encapsulation, for achieving a desired position of the plurality of die between the leads of the upper and lower lead frames in the packaged semiconductor. After the encapsulated die are separated, the upper leads have an L-shape and electrically couple die contacts on upper side of the die to leads on the lower side of the die so that the package contacts are on the same side of the semiconductor package.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: November 19, 2013
    Assignee: Vishay-Siliconix
    Inventors: Serge Jaunay, Suresh Belani, Frank Kuo, Sen Mao, Peter Wang
  • Publication number: 20120112331
    Abstract: A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing time.
    Type: Application
    Filed: September 9, 2011
    Publication date: May 10, 2012
    Applicant: SILICONIX ELECTRONIC CO., LTD.
    Inventors: Frank Kuo, Suresh Belani
  • Publication number: 20110175217
    Abstract: The present technology is directed toward semiconductors packaged by electrically coupling a plurality of die to an upper and lower lead frame. The opposite edges of each corresponding set of leads in the upper lead frame are bent. The leads in the upper lead frame are electrically coupled between respective contacts on respective die and respective lower portion of the leads in the lower lead frame. The bent opposite edges of each corresponding set of leads of the upper lead frame support the upper lead frame before encapsulation, for achieving a desired position of the plurality of die between the leads of the upper and lower lead frames in the packaged semiconductor. After the encapsulated die are separated, the upper leads have an L-shape and electrically couple die contacts on upper side of the die to leads on the lower side of the die so that the package contacts are on the same side of the semiconductor package.
    Type: Application
    Filed: March 24, 2010
    Publication date: July 21, 2011
    Applicant: VISHAY-SILICONIX
    Inventors: Serge Jaunay, Suresh Belani, Frank Kuo, Sen Mao, Peter Wang