Patents by Inventor Suresh Jagannathan

Suresh Jagannathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6496871
    Abstract: A distributed software system and method are provided for use with a plurality of potentially heterogeneous computer machines connected as a network. The system may comprise at least one agent comprising a protection domain, wherein the protection domain of the at least one agent resides on at least two of the plurality of computer machines. A plurality of objects is contained within the protection domain of the at least one agent, a first object residing on a first of the at least two computer machines and a second object residing on a second of the at least two computer machines. The objects are selectively movable among the at least two computer machines by a programmer of the system.
    Type: Grant
    Filed: June 30, 1998
    Date of Patent: December 17, 2002
    Assignees: NEC Research Institute, Inc., NEC Corporation
    Inventors: Suresh Jagannathan, Richard A. Kelsey, James F. Philbin, Satoru Fujita, Kazuya Koyama, Toru Yamanouchi
  • Patent number: 5745703
    Abstract: The system comprises a collection of address spaces within which potentially many concurrent lightweight perceptible threads may execute. The address space is uniformly distributed among different nodes in a network of heterogeneous machines. Address spaces are first-class and may be generated dynamically. Threads within an address space may communicate with one another via shared memory; communication between address spaces takes place using explicit message-passing.
    Type: Grant
    Filed: July 18, 1995
    Date of Patent: April 28, 1998
    Assignee: NEC Research Institute, Inc.
    Inventors: Henry Cejtin, Suresh Jagannathan, Richard A. Kelsey
  • Patent number: 5692193
    Abstract: A computer software architecture for controlling a highly parallel computer system comprises several layers of abstraction. The first layer is an abstract physical machine which contains a set of abstract physical processors. This layer may be considered as a microkernel. The next layer includes virtual machines and virtual processors. A virtual machine comprises a virtual address space and a set of virtual processors that are connected in a virtual topology. Virtual machines are mapped onto abstract physical machines with each virtual processor mapped onto an abstract physical processor. The third layer of abstraction defines threads. Threads are lightweight processes that run on virtual processors. In a preferred embodiment the abstract physical machines, abstract physical processors, virtual machines, virtual processors, thread groups, and threads are all first class objects.
    Type: Grant
    Filed: March 31, 1994
    Date of Patent: November 25, 1997
    Assignee: NEC Research Institute, Inc.
    Inventors: Suresh Jagannathan, James F. Philbin