Patents by Inventor Suresh Marisetty

Suresh Marisetty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7904751
    Abstract: Systems and methods for error handling are disclosed. The systems and methods may be utilized for single or multiple processor computer systems to handle errors in a coordinated manner between hardware and any firmware or software layers. A computer system includes a non volatile memory and at least one processor. A firmware error handling routine is stored on the non volatile memory. The firmware error handling routine is for handling errors. Each of the at least one processors detects errors. Each processor executes the firmware error handling routine on detecting an error. The executed firmware error handling routine handles the error. The executed firmware error handling routine also logs error information to a log. The systems and methods provide for coordinated error handling that enhance error recovery, provide error containment and maintain system availability.
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: March 8, 2011
    Assignee: Intel Corporation
    Inventors: Suresh Marisetty, Mani Ayyar, Nhon T. Quach, Bernard J. Lint
  • Patent number: 7721148
    Abstract: Disclosed is a communication mechanism among hardware, firmware and system software in order to redirect interrupts or other hardware events to only one thread execution context of an error domain for a multi-threaded processing system. Other embodiments are also described and claimed.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Scott Brenden, Suresh Marisetty, Kushagra Vaid
  • Patent number: 7546487
    Abstract: Methods and architectures for performing hardware error handling using coordinated operating system (OS) and firmware services. In one aspect, a firmware interface is provided to enable an OS to access firmware error-handling services. Such services enable the OS to access error data concerning platform hardware errors that may not be directed accessed via a platform processor or through other conventional approaches. Techniques are also disclosed for intercepting the processing of hardware error events and directing control to firmware error-handling services prior to attempting to service the error using OS-based services. The firmware services may correct hardware errors and/or log error data that may be later accessed by the OS or provided to a remote management server using an out-of-band communication channel. In accordance with another aspect, the firmware intercept and services may be performed in a manner that is transparent to the OS.
    Type: Grant
    Filed: September 15, 2005
    Date of Patent: June 9, 2009
    Assignee: Intel Corporation
    Inventors: Suresh Marisetty, Andrew J. Fish, Koichi Yamada, Scott D. Brenden, James B. Crossland, Shivnandan Kaushik, Mohan J. Kumar, Jose A. Vargas
  • Patent number: 7533300
    Abstract: Configurable error handling apparatus and methods to operate the same are disclosed. An example apparatus comprises a processor core in a semiconductor package, a hardware functional block in the semiconductor package, an error handler in the semiconductor package, wherein the error handler is configurable to route error data from the hardware functional block to at least one of a first error log or a second error log and to route error signals from the hardware functional block to at least one of an operating system or firmware, and wherein the processor core configures the error handler and the hardware functional block.
    Type: Grant
    Filed: February 13, 2006
    Date of Patent: May 12, 2009
    Assignee: Intel Corporation
    Inventors: Suresh Marisetty, Baskaran Ganesan, Gautam Bhagwandas Doshi, Murugasamy Nachimuthu, Koichi Yamada, Jose A. Vargas, Jim Crossland, Stan J. Domen
  • Patent number: 7502959
    Abstract: A system comprises a non volatile memory and a plurality of processors. The non volatile memory stores an error handling routine. Each processor of the plurality of processors accesses the error handling routine on detecting an error and, on certain errors, signals the remaining processors to enter a rendezvous state. In the rendezvous state, a single processor takes over and performs error handling.
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: March 10, 2009
    Assignee: Intel Corporation
    Inventors: Suresh Marisetty, George Thangadurai, Mani Ayyar
  • Patent number: 7353433
    Abstract: Use of data poisoning techniques may permit proactive operating system recovery without needing to always bringing down the operating system when uncorrectable errors are encountered.
    Type: Grant
    Filed: December 8, 2003
    Date of Patent: April 1, 2008
    Assignee: Intel Corporation
    Inventors: Kushagra Vaid, Suresh Marisetty, Yaron Shragai, Koichi Yamada, Rajendra Kuramkote, Scott Brenden
  • Publication number: 20080005615
    Abstract: Disclosed is a communication mechanism among hardware, firmware and system software in order to redirect interrupts or other hardware events to only one thread execution context of an error domain for a multi-threaded processing system. Other embodiments are also described and claimed.
    Type: Application
    Filed: June 29, 2006
    Publication date: January 3, 2008
    Inventors: Scott Brenden, Suresh Marisetty, Kushagra Vaid
  • Patent number: 7308610
    Abstract: A processing system may include an operating system (OS) and one or more specialized error handling modules to be registered with the OS after the processing system is powered on. The OS may also include a master policy module. The specialized error handling module may collect error data from a component of the processing system, and may generate abstracted error data, based at least in part on the collected error data. The master policy module may determine a recovery action to be taken, based at least in part on the abstracted error data. The OS may also include an error collection routine that calls one or more specialized error handling modules in response to detecting a hardware error. The error collection routine may also retrieve information from firmware in response to detecting the hardware error. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 10, 2004
    Date of Patent: December 11, 2007
    Assignee: Intel Corporation
    Inventors: Rajendra Kuramkote, Suresh Marisetty, Koichi Yamada, Scott Brenden, William Cheung
  • Publication number: 20070220332
    Abstract: Configurable error handling apparatus and methods to operate the same are disclosed. An example apparatus comprises a processor core in a semiconductor package, a hardware functional block in the semiconductor package, an error handler in the semiconductor package, wherein the error handler is configurable to route error data from the hardware functional block to at least one of a first error log or a second error log and to route error signals from the hardware functional block to at least one of an operating system or firmware, and wherein the processor core configures the error handler and the hardware functional block.
    Type: Application
    Filed: February 13, 2006
    Publication date: September 20, 2007
    Inventors: Suresh Marisetty, Baskaran Ganesan, Gautam Doshi, Murugasamy Nachimuthu, Koichi Yamada, Jose Vargas, Jim Crossland, Stan Domen
  • Publication number: 20070061634
    Abstract: Methods and architectures for performing hardware error handling using coordinated operating system (OS) and firmware services. In one aspect, a firmware interface is provided to enable an OS to access firmware error-handling services. Such services enable the OS to access error data concerning platform hardware errors that may not be directed accessed via a platform processor or through other conventional approaches. Techniques are also disclosed for intercepting the processing of hardware error events and directing control to firmware error-handling services prior to attempting to service the error using OS-based services. The firmware services may correct hardware errors and/or log error data that may be later accessed by the OS or provided to a remote management server using an out-of-band communication channel. In accordance with another aspect, the firmware intercept and services may be performed in a manner that is transparent to the OS.
    Type: Application
    Filed: September 15, 2005
    Publication date: March 15, 2007
    Inventors: Suresh Marisetty, Andrew Fish, Koichi Yamada, Scott Brenden, James Crossland, Shivnandan Kaushik, Mohan Kumar, Jose Vargas
  • Patent number: 7117396
    Abstract: A firmware-based mechanism for creating, storing and retrieving variable-length records associated with error events occurring in a computer platform. The mechanism responds to error notifications by invoking a firmware-based error-handling module. The error-handling module retrieves processor-specific error information and may also interrogate the other components of the computer platform to determine their error status. Then, according to the nature of the discovered errors, the error-handling module may assemble the retrieved error information and status information into a variable-length error record, which the error-handling module may then store in a memory. On request from a processing agent, the error-handling module may retrieve a previously-stored error record and present it to the requesting agent. Thus, the invention provides a unified and standardized approach to computer error handling at the firmware level.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: October 3, 2006
    Assignee: Intel Corporation
    Inventors: Eshwari P. Komarla, Suresh Marisetty, Mani Ayyar, Andrew J. Fish, Mohan J. Kumar, Shivnandan D. Kaushik
  • Publication number: 20060143515
    Abstract: A processing system may include an operating system (OS) and one or more specialized error handling modules to be registered with the OS after the processing system is powered on. The OS may also include a master policy module. The specialized error handling module may collect error data from a component of the processing system, and may generate abstracted error data, based at least in part on the collected error data. The master policy module may determine a recovery action to be taken, based at least in part on the abstracted error data. The OS may also include an error collection routine that calls one or more specialized error handling modules in response to detecting a hardware error. The error collection routine may also retrieve information from firmware in response to detecting the hardware error. Other embodiments are described and claimed.
    Type: Application
    Filed: December 10, 2004
    Publication date: June 29, 2006
    Inventors: Rajendra Kuramkote, Suresh Marisetty, Koichi Yamada, Scott Brenden, William Cheung
  • Publication number: 20060112307
    Abstract: A system and method for injecting hardware errors into a microprocessor system is described. In one embodiment, a software interface between system software and system firmware is established. Software test and debug for software error handlers may thus be supported. The software interface may support both a query mode call and a seed mode call. When a query mode call is issued, it may request whether or not the system firmware and hardware support the injection of a specified kind of error. A return from this call may be used to make a list of supported errors for injection. When a seed mode call is issued, the corresponding error may be injected into the hardware.
    Type: Application
    Filed: November 9, 2004
    Publication date: May 25, 2006
    Inventors: Suresh Marisetty, Rajendra Kuramkote, Koichi Yamada, Scott Brenden, Kushagra Vaid
  • Publication number: 20050138487
    Abstract: Use of data poisoning techniques may permit proactive operating system recovery without needing to always bringing down the operating system when uncorrectable errors are encountered.
    Type: Application
    Filed: December 8, 2003
    Publication date: June 23, 2005
    Applicant: Intel Corporation (a Delaware corporation)
    Inventors: Kushagra Vaid, Suresh Marisetty, Yaron Shragai, Koichi Yamada, Rajendra Kuramkote, Scott Brenden
  • Patent number: 6754828
    Abstract: A novel processor architecture and algorithms are provided which improve non-volatile memory updates and increases processor performance in successive generations of processors. A new processor architecture is supported by a software model consisting of two new firmware layers and the legacy 32 bit basic input output system (BIOS) firmware. The new firmware layers consist of a Processor Abstraction Layer (PAL) and a System Abstraction Layer (SAL). The PAL and SAL have procedure calls which allow updates of the firmware components in the non-volatile memory of a system, e.g. non-volatile ROM. The present invention includes invoking a system abstraction layer update procedure to implement a new input binary into the non-volatile memory. An algorithm for the non-volatile memory includes selecting a lead processor to perform an update and using the system abstraction layer update procedure. The system abstraction layer update procedure is used to call an appropriate authentication routine.
    Type: Grant
    Filed: July 13, 1999
    Date of Patent: June 22, 2004
    Assignee: Intel Corporation
    Inventors: Suresh Marisetty, Andrew J. Fish, Yan Li, Mani Ayyar, Amy O'Donnell, George Thangadurai, Sham M. Datta
  • Publication number: 20040095833
    Abstract: A system comprises a non volatile memory and a plurality of processors. The non volatile memory stores an error handling routine. Each processor of the plurality of processors accesses the error handling routine on detecting an error and, on certain errors, signals the remaining processors to enter a rendezvous state. In the rendezvous state, a single processor takes over and performs error handling.
    Type: Application
    Filed: July 28, 2003
    Publication date: May 20, 2004
    Applicant: Intel Corporation
    Inventors: Suresh Marisetty, George Thangadurai, Mani Ayyar
  • Publication number: 20040019835
    Abstract: Systems and methods for error handling are disclosed. The systems and methods may be utilized for single or multiple processor computer systems to handle errors in a coordinated manner between hardware and any firmware or software layers. A computer system includes a non volatile memory and at least one processor. A firmware error handling routine is stored on the non volatile memory. The firmware error handling routine is for handling errors. Each of the at least one processors detects errors. Each processor executes the firmware error handling routine on detecting an error. The executed firmware error handling routine handles the error. The executed firmware error handling routine also logs error information to a log.
    Type: Application
    Filed: July 28, 2003
    Publication date: January 29, 2004
    Applicant: Intel Corporation
    Inventors: Suresh Marisetty, Main Ayyar, Nhon T. Quach, Bernard J. Lint
  • Patent number: 6675324
    Abstract: A system comprises a non volatile memory and a plurality of processors. The non volatile memory stores an error handling routine. Each processor of the plurality of processors accesses the error handling routine on detecting an error and, on certain errors, signals the remaining processors to enter a rendezvous state. In the rendezvous state, a single processor takes over and performs error handling.
    Type: Grant
    Filed: September 27, 1999
    Date of Patent: January 6, 2004
    Assignee: Intel Corporation
    Inventors: Suresh Marisetty, George Thangadurai, Mani Ayyar
  • Patent number: 6622260
    Abstract: Systems and methods for error handling are disclosed. The systems and methods may be utilized for single or multiple processor computer systems to handle errors in a coordinated manner between hardware and any firmware or software layers. A computer system includes a non volatile memory and at least one processor. A firmware error handling routine is stored on the non volatile memory. The firmware error handling routine is for handling errors. Each of the at least one processors detects errors. Each processor executes the firmware error handling routine on detecting an error. The executed firmware error handling routine handles the error. The executed firmware error handling routine also logs error information to a log. The systems and methods provide for coordinated error handling that enhance error recovery, provide error containment and maintain system availability.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: September 16, 2003
    Inventors: Suresh Marisetty, Mani Ayyar, Nhon T. Quach, Bernard J. Lint
  • Publication number: 20030126516
    Abstract: A firmware-based mechanism for creating, storing and retrieving variable-length records associated with error events occurring in a computer platform. The mechanism responds to error notifications by invoking a firmware-based error-handling module. The error-handling module retrieves processor-specific error information and may also interrogate the other components of the computer platform to determine their error status. Then, according to the nature of the discovered errors, the error-handling module may assemble the retrieved error information and status information into a variable-length error record, which the error-handling module may then store in a memory. On request from a processing agent, the error-handling module may retrieve a previously-stored error record and present it to the requesting agent. Thus, the invention provides a unified and standardized approach to computer error handling at the firmware level.
    Type: Application
    Filed: December 28, 2001
    Publication date: July 3, 2003
    Inventors: Eshwari P. Komarla, Suresh Marisetty, Mani Ayyar, Andrew J. Fish, Mohan J. Kumar, Shivnandan D. Kaushik