Patents by Inventor Suriyakala Ramalingam

Suriyakala Ramalingam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11022792
    Abstract: Aspects of the embodiments are directed to coupling a permanent magnet (PM) with a microelectromechanical systems (MEMS) device. In embodiments, an adhesive, such as an epoxy or resin or other adhesive material, can be used to move the PM towards the MEMS device to magnetically couple the PM to the MEMS device. In embodiments, an adhesive that is configured to shrink up on curing can be applied (e.g., using a pick and place tool) to a location between the MEMS device and the PM. As a result of curing, the adhesive can pull the PM towards the MEMS device. In embodiments, an adhesive that is configured to expand as a result of curing can be applied to a location between the PM and a sidewall of the chassis. As a result of curing, the adhesive can push the PM towards the MEMS device. The adhesive can also secure the PM in place.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventors: Kyle Yazzie, Anna M. Prakash, Suriyakala Ramalingam, Liwei Wang, Robert Starkston, Arnab Choudhury, Sandeep S. Iyer, Amanuel M. Abebaw, Nick Labanok
  • Publication number: 20190391386
    Abstract: Aspects of the embodiments are directed to coupling a permanent magnet (PM) with a microelectromechanical systems (MEMS) device. In embodiments, an adhesive, such as an epoxy or resin or other adhesive material, can be used to move the PM towards the MEMS device to magnetically couple the PM to the MEMS device. In embodiments, an adhesive that is configured to shrink up on curing can be applied (e.g., using a pick and place tool) to a location between the MEMS device and the PM. As a result of curing, the adhesive can pull the PM towards the MEMS device. In embodiments, an adhesive that is configured to expand as a result of curing can be applied to a location between the PM and a sidewall of the chassis. As a result of curing, the adhesive can push the PM towards the MEMS device. The adhesive can also secure the PM in place.
    Type: Application
    Filed: December 27, 2016
    Publication date: December 26, 2019
    Applicant: Intel Corporation
    Inventors: Kyle Yazzie, Anna M. Prakash, Suriyakala Ramalingam, Liwei Wang, Robert Starkston, Arnab Choudhury, Sandeep S. Iyer, Amanuel M. Abebaw, Nick Labanok
  • Patent number: 10356912
    Abstract: An electronic system includes a printed circuit board (PCB), a component affixed to the PCB, and a conformal coating layer on the PCB and the component. The conformal coating layer includes parylene. Furthermore, the electronic system includes an underfill layer adjacent to the conformal coating layer, filling a gap between the PCB and the component. Other embodiments being described and/or claimed.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: July 16, 2019
    Assignee: Intel Corporation
    Inventors: Priyanka Dobriyal, Suriyakala Ramalingam, Chester C. Lee, Raiyomand F. Aspandiar
  • Patent number: 10317952
    Abstract: An apparatus is provided which comprises: a chassis compartment having a bottom surface and walls orthogonal to the bottom, wherein the chassis compartment comprises: a rectangular opening, which may be designed to accept a microelectromechanical (MEMS) device and four slots, which may be designed to accept one or more magnet(s), extending outwardly from the rectangular opening, wherein each of the slots comprises: an inner opening having a length coextensive with a side of the rectangular opening, and an outer opening having corresponding ends that extend a length of the outer opening beyond the length of the inner opening. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventors: Sandeep S. Iyer, Amanuel Abebaw, Mark Saltas, Mayank Patel, Charavana K. Gurumurthy, Suriyakala Ramalingam, Vladimir Malamud
  • Patent number: 10269695
    Abstract: A method for forming an electrical device includes attaching a semiconductor die on a carrier. The method further includes dispensing a fillet material at at least one edge of the semiconductor die arranged on the carrier. The method further includes dispensing an underfill material into a gap between the semiconductor die and the carrier after dispensing the fillet material.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: April 23, 2019
    Assignee: Intel Corporation
    Inventors: Robert F. Cheney, Ashish Dhall, Suriyakala Ramalingam
  • Publication number: 20180342463
    Abstract: In various embodiments this disclosure is directed to conductive adhesives layers that can be used, in one example embodiment, to connect one or more shielding structures (for example, metal cans and/or covers) to a semiconductor package to enclose one or more electronic components on the semiconductor package. In another embodiment, the conductive adhesive layers disclosed herein can be used in connection with optoelectronic devices (for example, optoelectronic devices including laser diodes and/or avalanche photodiodes, APDs). In one embodiment, the conductive adhesives can additionally be used for thermal dissipation and for electrical contact in connection with one or more electronic components on a semiconductor package. In one embodiment, various materials including, spray prints, conductive paste, inks (for example, sintering silver-based materials), epoxy material (for example, epoxy materials filled with silver and/or other metal particles) can be used to provide a conductive adhesive layer.
    Type: Application
    Filed: July 13, 2018
    Publication date: November 29, 2018
    Inventors: Taylor GAINES, Anna M. PRAKASH, Suriyakala RAMALINGAM, Boxi LIU, Mohit GUPTA, Ziv BELMAN, Baruch SCHIFFMANN, Arnon HIRSHBERG, Vladimir MALAMUD, Ron WITTENBERG
  • Publication number: 20180324955
    Abstract: An apparatus is described. The apparatus includes a first planar board to second planar board interface. The first planar board to second planar board interface includes a reflowed solder electrical connection structure between the first and second boards and a no flow adhesive. The reflowed solder electrical connection structure includes a reflowed solder ball and a reflowed tinned pad.
    Type: Application
    Filed: December 23, 2015
    Publication date: November 8, 2018
    Inventors: Mohit SOOD, Huili XU, Wei TAN, Suriyakala RAMALINGAM, Jan KRAJNIAK, Nish ANANTHAKRISHNAN
  • Patent number: 10115606
    Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include modifying an underfill material with one of a thiol adhesion promoter, an azole coupling agent, surface modified filler, and peroxide based cross-linking polymer chemistries to greatly enhance adhesion in package structures utilizing the embodiments herein.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: October 30, 2018
    Assignee: Intel Corporation
    Inventors: Yiqun Bai, Yuying Wei, Arjun Krishnan, Suriyakala Ramalingam, Yonghao Xiu, Beverly J. Canham, Sivakumar Nagarajan, Saikumar Jayaraman, Nisha Ananthakrishnan
  • Publication number: 20180190593
    Abstract: In various embodiments this disclosure is directed to conductive adhesives layers that can be used, in one example embodiment, to connect one or more shielding structures (for example, metal cans and/or covers) to a semiconductor package to enclose one or more electronic components on the semiconductor package. In another embodiment, the conductive adhesive layers disclosed herein can be used in connection with optoelectronic devices (for example, optoelectronic devices including laser diodes and/or avalanche photodiodes, APDs). In one embodiment, the conductive adhesives can additionally be used for thermal dissipation and for electrical contact in connection with one or more electronic components on a semiconductor package. In one embodiment, various materials including, spray prints, conductive paste, inks (for example, sintering silver-based materials), epoxy material (for example, epoxy materials filled with silver and/or other metal particles) can be used to provide a conductive adhesive layer.
    Type: Application
    Filed: December 30, 2016
    Publication date: July 5, 2018
    Inventors: Taylor GAINES, Anna M. PRAKASH, Suriyakala RAMALINGAM, Boxi LIU, Mohit GUPTA, Ziv BELMAN, Baruch SCHIFFMANN, Arnon HIRSHBERG, Vladimir MALAMUD, Ron WITTENBERG
  • Publication number: 20180095503
    Abstract: An apparatus is provided which comprises: a chassis compartment having a bottom surface and walls orthogonal to the bottom, wherein the chassis compartment comprises: a rectangular opening, which may be designed to accept a microelectromechanical (MEMS) device and four slots, which may be designed to accept one or more magnet(s), extending outwardly from the rectangular opening, wherein each of the slots comprises: an inner opening having a length coextensive with a side of the rectangular opening, and an outer opening having corresponding ends that extend a length of the outer opening beyond the length of the inner opening. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: September 30, 2016
    Publication date: April 5, 2018
    Inventors: Sandeep S. IYER, Amanuel ABEBAW, Mark SALTAS, Mayank PATEL, Charavana K. GURUMURTHY, Suriyakala RAMALINGAM, Vladimir MALAMUD
  • Publication number: 20180070456
    Abstract: An electronic system may include a printed circuit board (PCB), a component affixed to the PCB, and a conformal coating layer on the PCB and the component. The conformal coating layer may include parylene. Furthermore, the electronic system may include an underfill layer adjacent to the conformal coating layer, filling a gap between the PCB and the component. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 6, 2016
    Publication date: March 8, 2018
    Inventors: Priyanka Dobriyal, Suriyakala Ramalingam, Chester C. Lee, Raiyomand F. Aspandiar
  • Publication number: 20170263517
    Abstract: A method for forming an electrical device includes attaching a semiconductor die on a carrier. The method further includes dispensing a fillet material at at least one edge of the semiconductor die arranged on the carrier. The method further includes dispensing an underfill material into a gap between the semiconductor die and the carrier after dispensing the fillet material.
    Type: Application
    Filed: May 26, 2017
    Publication date: September 14, 2017
    Inventors: Robert F. Cheney, Ashish Dhall, Suriyakala Ramalingam
  • Patent number: 9704767
    Abstract: Techniques and mechanisms for mitigating warpage of structures in a package. In an embodiment, a packaged integrated circuit device includes a mold compound disposed at least partially around an integrated circuit chip. The mold compound comprises fibers suspended in a media that is to aid in mechanical reinforcement of such fibers. The reinforced fibers contribute to mold compound properties that resist warping of the IC chip that might otherwise take place as a result of solder reflow or other processing. A modulus of elasticity of the mold compound is equal to or more than three GigePascals (3 GPa), where the modulus of elasticity corresponds to a temperature equal to two hundred and sixty degrees Celsius (260° C.). In another embodiment, a spiral flow value of the mold compound is equal to or more than sixty five centimeters (65 cm).
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: July 11, 2017
    Assignee: Intel Corporation
    Inventors: Suriyakala Ramalingam, Yiqun Bai, Nisha Ananthakrishnan, Arjun Krishnan
  • Publication number: 20170186658
    Abstract: Techniques and mechanisms for mitigating warpage of structures in a package. In an embodiment, a packaged integrated circuit device includes a mold compound disposed at least partially around an integrated circuit chip. The mold compound comprises fibers suspended in a media that is to aid in mechanical reinforcement of such fibers. The reinforced fibers contribute to mold compound properties that resist warping of the IC chip that might otherwise take place as a result of solder reflow or other processing. A modulus of elasticity of the mold compound is equal to or more than three GigePascals (3 GPa), where the modulus of elasticity corresponds to a temperature equal to two hundred and sixty degrees Celsius (260° C.). In another embodiment, a spiral flow value of the mold compound is equal to or more than sixty five centimeters (65 cm).
    Type: Application
    Filed: December 23, 2015
    Publication date: June 29, 2017
    Inventors: Suriyakala RAMALINGAM, Yiqun BAI, Nisha ANANTHAKRISHNAN, Arjun KRISHNAN
  • Patent number: 9691675
    Abstract: A method for forming an electrical device includes attaching a semiconductor die on a carrier. The method further includes dispensing a fillet material at at least one edge of the semiconductor die arranged on the carrier. The method further includes dispensing an underfill material into a gap between the semiconductor die and the carrier after dispensing the fillet material.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: June 27, 2017
    Assignee: Intel Corporation
    Inventors: Robert F Cheney, Ashish Dhall, Suriyakala Ramalingam
  • Publication number: 20170178988
    Abstract: A method for forming an electrical device includes attaching a semiconductor die on a carrier. The method further includes dispensing a fillet material at at least one edge of the semiconductor die arranged on the carrier. The method further includes dispensing an underfill material into a gap between the semiconductor die and the carrier after dispensing the fillet material.
    Type: Application
    Filed: December 22, 2015
    Publication date: June 22, 2017
    Inventors: Robert F Cheney, Ashish Dhall, Suriyakala Ramalingam
  • Publication number: 20160343591
    Abstract: Embodiments of the present disclosure are directed to techniques and configurations for an integrated circuit (IC) package having an underfill layer with filler particles arranged in a generally random distribution pattern. In some embodiments, a generally random distribution pattern of filler particles may be obtained by reducing an electrostatic charge on one or more components of the IC package assembly, by applying a surface treatment to filler to reduce filler electrical charge, by applying an electric force against the filler particles of the underfill material in a direction opposite to a direction of gravitational force, by using an underfill material with a relatively low maximum filler particle size, and/or by snap curing the underfill layer at a relatively low temperature. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: August 1, 2016
    Publication date: November 24, 2016
    Inventors: Suriyakala Ramalingam, Manish Dubey, Hsin-Yu Li, Michelle S. Phen-Givoni, Hitesh Arora, Nisha Ananthakrishnan, Yiqun Bai, Yonghao Xiu, Rajendra C. Dias
  • Publication number: 20160268213
    Abstract: An apparatus including a package including a die and a package substrate, the package substrate including a conductor; and a stiffener body electrically coupled to the conductor of the package substrate. An apparatus including a package including a die and a package substrate; a stiffener body coupled to the package substrate; and an electrically conductive path between the stiffener body and the package substrate. A method including electrically coupling a stiffener body to a conductor of a package substrate.
    Type: Application
    Filed: March 9, 2015
    Publication date: September 15, 2016
    Inventors: Hongjin JIANG, Robert STARKSTON, Digvijay A. RAORANE, Keith D. JONES, Ashish DHALL, Omkar G. KARHADE, Kedar DHANE, Suriyakala RAMALINGAM, Li-Sheng WENG, Robert F. CHENEY, Patrick N. STOVER
  • Patent number: 9431274
    Abstract: Embodiments of the present disclosure are directed to techniques and configurations for an integrated circuit (IC) package having an underfill layer with filler particles arranged in a generally random distribution pattern. In some embodiments, a generally random distribution pattern of filler particles may be obtained by reducing an electrostatic charge on one or more components of the IC package assembly, by applying a surface treatment to filler to reduce filler electrical charge, by applying an electric force against the filler particles of the underfill material in a direction opposite to a direction of gravitational force, by using an underfill material with a relatively low maximum filler particle size, and/or by snap curing the underfill layer at a relatively low temperature. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: August 30, 2016
    Assignee: Intel Corporation
    Inventors: Suriyakala Ramalingam, Manish Dubey, Hsin-Yu Li, Michelle S. Phen, Hitesh Arora, Nisha Ananthakrishnan, Yiqun Bai, Yonghao Xiu, Rajendra C. Dias
  • Publication number: 20160240395
    Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include modifying an underfill material with one of a thiol adhesion promoter, an azole coupling agent, surface modified filler, and peroxide based cross-linking polymer chemistries to greatly enhance adhesion in package structures utilizing the embodiments herein.
    Type: Application
    Filed: April 26, 2016
    Publication date: August 18, 2016
    Inventors: Yiqun Bai, Yuying Wei, Arjun Krishnan, Suriyakala Ramalingam, Yonghao Xiu, Beverly J. Canham, Sivakumar Nagarajan, Saikumar Jayaraman, Nisha Ananthakrishnan