Abstract: Providing fairness-based allocation of caches in processor-based devices is disclosed. In some aspects, a processor-based device comprises a processor that comprises a cache. The processor is configured to determine a fairness index for a client of a plurality of clients of the cache. The processor is further configured to allocate a portion of the cache for use by the client based on the fairness index. The processor is also configured to receive data to be written to the cache, wherein the data corresponds to the client. The processor is additionally configured to write the data to a cache line within the cache based on the portion of the cache allocated to the client.

Abstract: Providing adaptive cache bypass in processor-based devices is disclosed. In some aspects, a processor-based device comprises a processor that comprises a cache. The processor is configured to calculate a cache result rate based on a first one or more outcomes of a corresponding first one or more cache requests to a cache region of the cache during a sampling period. The processor is further configured to determine that the cache result rate fails to satisfy a cache result requirement. The processor is also configured to, responsive to determining that the cache result rate fails to satisfy the cache result requirement, restrict access to the cache region of the cache subsequent to the sampling period.

Abstract: Stride-based prefetcher circuits for prefetching data for next stride(s) of a cache read request into a cache memory based on identified stride patterns in the cache read request, and related processor-based systems and methods are disclosed. A stride-based prefetcher circuit (“prefetcher circuit”) observes cache read requests to a cache memory in run-time to determine if a stride pattern exists. In response to detecting a stride pattern, the prefetcher circuit prefetches data from next memory location(s) in the detected stride from higher-level memory, and loads the prefetch data into the cache memory. This is because there is a higher likelihood that when a stride in the cache read requests to the cache memory is detected to exist, subsequent cache read requests to the cache memory will more likely than not continue with the same stride. The cache hit rate of the cache memory may be increased as a result.

Abstract: Apparatuses and method for an integrated circuit device are described. In an apparatus thereof, there is a plurality of memory controllers coupled to a plurality of memory banks. A network of switches is coupled to the plurality of memory controllers. A plurality of data processing devices is coupled to the network of switches and is configured to generate memory requests. A network controller is coupled to the network of switches and is configured to queue the memory requests and selectively issue requests to memory from the memory requests queued responsive to corresponding response times associated with the plurality of memory banks.

Abstract: Apparatuses and method for an integrated circuit device are described. In an apparatus thereof, there is a plurality of memory controllers coupled to a plurality of memory banks. A network of switches is coupled to the plurality of memory controllers. A plurality of data processing devices is coupled to the network of switches and is configured to generate memory requests. A network controller is coupled to the network of switches and is configured to queue the memory requests and selectively issue requests to memory from the memory requests queued responsive to corresponding response times associated with the plurality of memory banks.

Abstract: The disclosed embodiments relate to a method for dynamically changing a prefetching configuration in a computer system, wherein the prefetching configuration specifies how to change an ahead distance that specifies how many references ahead to prefetch for each stream. During operation of the computer system, the method keeps track of one or more stream lengths, wherein a stream is a sequence of memory references with a constant stride. Next, the method dynamically changes the prefetching configuration for the computer system based on observed stream lengths in a most-recent window of time.

Abstract: The disclosed embodiments relate to a method for dynamically changing a prefetching configuration in a computer system, wherein the prefetching configuration specifies how to change an ahead distance that specifies how many references ahead to prefetch for each stream. During operation of the computer system, the method keeps track of one or more stream lengths, wherein a stream is a sequence of memory references with a constant stride. Next, the method dynamically changes the prefetching configuration for the computer system based on observed stream lengths in a most-recent window of time.