Abstract: Devices and methods of providing hardware support for dynamic type checking are provided. In some embodiments, a processor includes a type check register and support for one or more checked load instructions. In some embodiments, normal load instructions are replaced by a compiler with the checked load instructions. In some embodiments, to perform a checked load, an error handler instruction location is stored in the type check register, and a type tag operand is compared to a type tag stored in the loaded memory location. If the comparison succeeds, execution may proceed normally. If the comparison fails, execution may be transferred to the error handler instruction. In some embodiments, type prediction is performed to determine whether a checked load instruction is likely to fail.

Abstract: A dataflow instruction set architecture and execution model, referred to as WaveScalar, which is designed for scalable, low-complexity/high-performance processors, while efficiently providing traditional memory semantics through a mechanism called wave-ordered memory. Wave-ordered memory enables “real-world” programs, written in any language, to be run on the WaveScalar architecture, as well as any out-of-order execution unit. Because it is software-controlled, wave-ordered memory can be disabled to obtain greater parallelism. Wavescalar also includes a software-controlled tag management system.

Abstract: Devices and methods of providing hardware support for dynamic type checking are provided. In some embodiments, a processor includes a type check register and support for one or more checked load instructions. In some embodiments, normal load instructions are replaced by a compiler with the checked load instructions. In some embodiments, to perform a checked load, an error handler instruction location is stored in the type check register, and a type tag operand is compared to a type tag stored in the loaded memory location. If the comparison succeeds, execution may proceed normally. If the comparison fails, execution may be transferred to the error handler instruction. In some embodiments, type prediction is performed to determine whether a checked load instruction is likely to fail.

Abstract: A dataflow instruction set architecture and execution model, referred to as WaveScalar, which is designed for scalable, low-complexity/high-performance processors, while efficiently providing traditional memory semantics through a mechanism called wave-ordered memory. Wave-ordered memory enables “real-world” programs, written in any language, to be run on the WaveScalar architecture, as well as any out-of-order execution unit. Because it is software-controlled, wave-ordered memory can be disabled to obtain greater parallelism. Wavescalar also includes a software-controlled tag management system.

Abstract: A dataflow instruction set architecture and execution model, referred to as WaveScalar, which is designed for scalable, low-complexity/high-performance processors, while efficiently providing traditional memory semantics through a mechanism called wave-ordered memory. Wave-ordered memory enables “real-world” programs, written in any language, to be run on the WaveScalar architecture, as well as any out-of-order execution unit. Because it is software-controlled, wave-ordered memory can be disabled to obtain greater parallelism. Wavescalar also includes a software-controlled tag management system.

Abstract: Selective dynamic compilation of source code is performed using run-time information. A system is disclosed that implements a declarative, annotation based dynamic compilation of the source code, employing a partial evaluation, binding-time analysis (BTA), and including program-point-specific polyvariant division and specialization and dynamic versions of traditional global and peephole optimizations. The system allows programmers to declaratively specify policies that govern the aggressiveness of specialization and caching, providing fine control over the dynamic compilation process. The policies include directions for controlling specialization at promotion points and merge points, and further define caching policies, and speculative-specialization policies. The system also enables programmers to specialize programs across arbitrary edges, both at traditional locations, such as procedure boundaries, but also within procedures.

Abstract: A system and a method is described for freeing renaming registers that have been allocated to architectural registers prior to another instruction redefining the architectural register. Renaming registers are used by a processor to dynamically execute instructions out-of-order. The present invention may be employed by any single or multi-threaded processor that executes instructions out-of-order. A mechanism is described for freeing renaming registers that consists of a set of instructions, used by a compiler, to indicate to the processor when it can free the physical (renaming) register that is allocated to a particular architectural register. This mechanism permits the renaming register to be reassigned or reallocated to store another value as soon as the renaming register is no longer needed for allocation to the architectural register.

Abstract: A system and a method is described for freeing renaming registers that have been allocated to architectural registers prior to another instruction redefining the architectural register. Renaming registers are used by a processor to dynamically execute instructions out-of-order. The present invention may be employed by any single or multi-threaded processor that executes instructions out-of-order. A mechanism is described for freeing renaming registers that consists of a set of instructions, used by a compiler, to indicate to the processor when it can free the physical (renaming) register that is allocated to a particular architectural register. This mechanism permits the renaming register to be reassigned or reallocated to store another value as soon as the renaming register is no longer needed for allocation to the architectural register.

Abstract: A method and organization for implementing the registers required in a computer system supporting multithreading and dynamic out-of-order execution. Multithreaded computer systems are those in which the processor supports multiple contexts (threads), and either rapid context switching from thread to thread or scheduling of instructions from different threads within a single cycle. An important component of processors for such systems is the register file; the processor needs a large register file or resource to provide the registers used for the threads. One form of the invention maintains a set of private architecturally specified registers, and a set of private renaming register for each different thread. In the other three embodiments, sharing of renaming registers between different threads is permitted, to enable a reduction in the total number of registers required.