Patents by Inventor Susan L. Feindt

Susan L. Feindt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200286997
    Abstract: A metal-oxide semiconductor field effect transistor (MOSFET) includes a source region and a drain region of a first conductivity type. The MOSFET additionally include a body region of a second conductivity type, where the body region underlies at least a portion of the source region and the drain region. The MOSFET further includes a buried region of the first conductivity type, where the buried region is disposed between the body region and a substrate, where the buried region is configured to reduce a capacitance between the source region and the drain region in response to an indicated voltage applied between the body region and the buried region.
    Type: Application
    Filed: March 5, 2019
    Publication date: September 10, 2020
    Inventors: Pengfei Wu, Susan L. Feindt, F. Jacob Steigerwald
  • Patent number: 10522389
    Abstract: A transfer printing method provides a first wafer having a receiving surface, and removes a second die from a second wafer using a die moving member. Next, the method positions the second die on the receiving surface of the first wafer. Specifically, to position the second die on the receiving surface, the first wafer has alignment structure for at least in part controlling movement of the die moving member.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: December 31, 2019
    Assignee: Analog Devices, Inc.
    Inventors: James Fiorenza, F. Jacob Steigerwald, Edward F. Gleason, Susan L. Feindt
  • Patent number: 5594266
    Abstract: An ESD protective clamp device comprised of a two-terminal diode formed in an isolated chip cell. The lower part of this chip cell region contains a buried layer of silicon with P-type dopant, and the upper part is an epitaxial layer also with P-type dopant. An annular (ring-shaped) anode plug segment is formed at the outer reaches of the epitaxial layer with P+ doping. At the interior central region is an N-type plug circular in horizontal cross-section and concentric with the annular plug. This central plug serves as the cathode. Electrical connections are made to anode and cathode to provide interconnection with an IC circuit with a MOM capacitor to be protected.
    Type: Grant
    Filed: October 20, 1995
    Date of Patent: January 14, 1997
    Assignee: Analog Devices, Incorporated
    Inventors: David F. Beigel, William A. Krieger, Susan L. Feindt
  • Patent number: 5477078
    Abstract: An ESD protective clamp device comprised of a two-terminal diode formed in an isolated chip cell. The lower part of this chip cell region contains a buried layer of silicon with P-type dopant, and the upper part is an epitaxial layer also with P-type dopant. An annular (ring-shaped) anode plug segment is formed at the outer reaches of the epitaxial layer with P+ doping. At the interior central region is an N-type plug circular in horizontal cross-section and concentric with the annular plug. This central plug serves as the cathode. Electrical connections are made to anode and cathode to provide interconnection with an IC circuit with a MOM capacitor to be protected.
    Type: Grant
    Filed: December 23, 1994
    Date of Patent: December 19, 1995
    Assignee: Analog Devices, Incorporated
    Inventors: David F. Beigel, William A. Krieger, Susan L. Feindt