Patents by Inventor Susmit Singha Roy
Susmit Singha Roy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230207314Abstract: Transition metal dichalcogenide films and methods for depositing transition metal dichalcogenide films on a substrate are described. Methods for converting transition metal oxide films to transition metal dichalcogenide films are also described. The substrate is exposed to a metal precursor and an oxidant to form a transition metal oxide film; the transition metal oxide film is exposed to a chalcogenide precursor to form the transition metal dichalcogenide film.Type: ApplicationFiled: December 27, 2021Publication date: June 29, 2023Applicant: Applied Materials, Inc.Inventors: Chandan Das, Susmit Singha Roy, Bhaskar Jyoti Bhuyan, Supriya Ghosh, Jiecong Tang, John Sudijono, Abhijit Basu Mallick, Mark Saly
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Publication number: 20230127535Abstract: Embodiments disclosed herein include methods of depositing a metal oxo photoresist using dry deposition processes. In an embodiment, the method comprises forming a first metal oxo film on the substrate with a first vapor phase process including a first metal precursor vapor and a first oxidant vapor, and forming a second metal oxo film over the first metal oxo film with a second vapor phase process including a second metal precursor vapor and a second oxidant vapor.Type: ApplicationFiled: December 16, 2022Publication date: April 27, 2023Inventors: Lakmal Charidu Kalutarage, Mark Joseph Saly, Bhaskar Jyoti Bhuyan, Thomas Joseph Knisley, Kelvin Chan, Regina Gemanie Freed, David Michael Thompson, Susmit Singha Roy, Madhur Sachan
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Publication number: 20230105408Abstract: Exemplary semiconductor processing methods may include providing a boron-containing precursor and a nitrogen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include forming a plasma of the boron-containing precursor and the nitrogen-containing precursor in the processing region. A temperature of the substrate may be maintained at less than or about 500° C. The methods may include forming a layer of material on the substrate. The layer of material may include hexagonal boron nitride. The methods include subsequent forming the layer of material on the substrate for a first period of time, halting delivery of the boron-containing precursor. The methods may include maintaining a flow of the nitrogen-containing precursor for a second period of time, and increasing a plasma power while maintaining the flow of the nitrogen-containing precursor.Type: ApplicationFiled: September 13, 2022Publication date: April 6, 2023Applicant: Applied Materials, Inc.Inventors: Zeqing Shen, Susmit Singha Roy, Abhijit Basu Mallick
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Publication number: 20230090280Abstract: Exemplary semiconductor processing methods may include providing a carbon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The substrate may include a low dielectric constant material defining one or more features, a liner extending across the low dielectric constant material and within the one or more features, and a metal-containing layer deposited on the liner and extending within the one or more features. The methods may include forming a layer of material on at least a portion of the liner and the metal-containing layer. The layer of material may include graphene. The methods may include removing substantially all of the portion of the layer of material on the liner.Type: ApplicationFiled: September 23, 2021Publication date: March 23, 2023Applicant: Applied Materials, Inc.Inventors: Supriya Ghosh, Susmit Singha Roy, Abhijit Basu Mallick
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Publication number: 20230090426Abstract: Exemplary semiconductor processing methods may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include forming a plasma of the silicon-containing precursor in the processing region and forming a first layer of material on the substrate. The first layer of material may include silicon oxide. The methods may include providing a germanium-containing precursor to the processing region of the semiconductor processing chamber and forming a plasma of the germanium-containing precursor in the processing region. Forming the plasma of the germanium-containing precursor may be performed at a plasma power of greater than or about 500 W. The methods may include forming a second layer of material on the substrate. The second layer of material may include germanium oxide.Type: ApplicationFiled: September 19, 2022Publication date: March 23, 2023Applicant: Applied Materials, Inc.Inventors: Sieun Chae, Susmit Singha Roy, Abhijit Basu Mallick
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Patent number: 11594415Abstract: Methods of forming a tungsten film comprising forming a boron seed layer on an oxide surface, an optional tungsten initiation layer on the boron seed layer and a tungsten containing film on the boron seed layer or tungsten initiation layer are described. Film stack comprising a boron seed layer on an oxide surface with an optional tungsten initiation layer and a tungsten containing film are also described.Type: GrantFiled: November 11, 2019Date of Patent: February 28, 2023Assignee: Applied Materials, Inc.Inventors: Susmit Singha Roy, Pramit Manna, Rui Cheng, Abhijit Basu Mallick
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Publication number: 20230056280Abstract: Exemplary methods of semiconductor processing may include delivering a carbon-containing precursor and a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. The methods may include generating a plasma of the carbon-containing precursor and the hydrogen-containing precursor within the processing region of the semiconductor processing chamber. The methods may include forming a layer of graphene on a substrate positioned within the processing region of the semiconductor processing chamber. The substrate may be maintained at a temperature below or about 600° C. The methods may include halting flow of the carbon-containing precursor while maintaining the plasma with the hydrogen-containing precursor.Type: ApplicationFiled: October 27, 2022Publication date: February 23, 2023Applicant: Applied Materials, Inc.Inventors: Jialiang Wang, Susmit Singha Roy, Abhijit Basu Mallick, Nitin K. Ingle
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Publication number: 20230059788Abstract: Exemplary methods of semiconductor processing may include etching one or more features partially through a dielectric material to expose material from one or more layer pairs formed on a substrate. The methods may include halting the etching prior to penetrating fully through the dielectric material, and prior to exposing material from all layer pairs formed on the substrate. The methods may include forming a layer of carbon-containing material on the exposed material from each of the one or more layer pairs having exposed material. The methods may include etching the one or more features fully through the dielectric material to expose material for each remaining layer pair formed on the substrate.Type: ApplicationFiled: August 20, 2021Publication date: February 23, 2023Applicant: Applied Materials, Inc.Inventors: Bhaskar Jyoti Bhuyan, Zeqing Shen, Susmit Singha Roy, Abhijit Basu Mallick
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Publication number: 20230057258Abstract: Exemplary methods of semiconductor processing may include forming a layer of carbon-containing material on a substrate disposed within a processing region of a semiconductor processing chamber. The substrate may include an exposed region of a first dielectric material and an exposed region of a metal-containing material. The layer of carbon-containing material may be selectively formed over the exposed region of the metal-containing material. Forming the layer of carbon-containing material may include one or more cycles of providing a first molecular species that selectively couples with the metal-containing material. Forming the layer of carbon-containing material may include providing a second molecular species that selectively couples with the first molecular species. The methods may include selectively depositing a second dielectric material on the exposed region of the first dielectric material.Type: ApplicationFiled: August 20, 2021Publication date: February 23, 2023Applicant: Applied Materials, Inc.Inventors: Bhaskar Jyoti Bhuyan, Zeqing Shen, Susmit Singha Roy, Abhijit Basu Mallick
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Publication number: 20230058831Abstract: Exemplary methods of semiconductor processing may include etching one or more features partially through a stack of layers formed on a substrate. The methods may include halting the etching prior to penetrating fully through the stack of layers formed on the substrate. The methods may include forming a layer of carbon-containing material along the stack of layers on the substrate. The layer of carbon-containing material may include a metal. The methods may include etching the one or more features fully through the stack of layers on the substrate.Type: ApplicationFiled: August 20, 2021Publication date: February 23, 2023Applicant: Applied Materials, Inc.Inventors: Bhaskar Jyoti Bhuyan, Zeqing Shen, Susmit Singha Roy, Abhijit Basu Mallick
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Patent number: 11562904Abstract: Embodiments disclosed herein include methods of depositing a metal oxo photoresist using dry deposition processes. In an embodiment, the method comprises forming a first metal oxo film on the substrate with a first vapor phase process including a first metal precursor vapor and a first oxidant vapor, and forming a second metal oxo film over the first metal oxo film with a second vapor phase process including a second metal precursor vapor and a second oxidant vapor.Type: GrantFiled: July 21, 2020Date of Patent: January 24, 2023Assignee: Applied Materials, Inc.Inventors: Lakmal Charidu Kalutarage, Mark Joseph Saly, Bhaskar Jyoti Bhuyan, Thomas Joseph Knisley, Kelvin Chan, Regina Germanie Freed, David Michael Thompson, Susmit Singha Roy, Madhur Sachan
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Patent number: 11545504Abstract: Methods and apparatus for forming a plurality of nonvolatile memory cells are provided herein. In some embodiments, the method, for example, includes forming a plurality of nonvolatile memory cells, comprising forming, on a substrate, a stack of alternating layers of metal including a first layer of metal and a second layer of metal different from the first layer of metal; removing the first layer of metal to form spaces between the alternating layers of the second layer of metal; and one of depositing a first layer of material to partially fill the spaces to leave air gaps therein or depositing a second layer of material to fill the spaces.Type: GrantFiled: April 12, 2021Date of Patent: January 3, 2023Assignee: APPLIED MATERIALS, INC.Inventors: Takehito Koshizawa, Mukund Srinivasan, Tomohiko Kitajima, Chang Seok Kang, Sung-Kwan Kang, Gill Y. Lee, Susmit Singha Roy
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Publication number: 20220411918Abstract: Transition metal dichalcogenide films and methods for depositing transition metal dichalcogenide films on a substrate are described. Methods for converting transition metal oxide films to transition metal dichalcogenide films are also described. The substrate is exposed to a precursor and a chalcogenide reactant to form the transition metal dichalcogenide film. The exposures can be sequential or simultaneous.Type: ApplicationFiled: June 28, 2021Publication date: December 29, 2022Applicant: Applied Materials, Inc.Inventors: Chandan Das, Susmit Singha Roy, Bhaskar Jyoti Bhuyan, John Sudijono, Abhijit Basu Mallick, Mark Saly
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Patent number: 11515163Abstract: Exemplary methods of semiconductor processing may include delivering a carbon-containing precursor and a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. The methods may include generating a plasma of the carbon-containing precursor and the hydrogen-containing precursor within the processing region of the semiconductor processing chamber. The methods may include forming a layer of graphene on a substrate positioned within the processing region of the semiconductor processing chamber. The substrate may be maintained at a temperature below or about 600° C. The methods may include halting flow of the carbon-containing precursor while maintaining the plasma with the hydrogen-containing precursor.Type: GrantFiled: January 6, 2021Date of Patent: November 29, 2022Assignee: Applied Materials, Inc.Inventors: Jialiang Wang, Susmit Singha Roy, Abhijit Basu Mallick, Nitin K. Ingle
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Publication number: 20220375750Abstract: Exemplary methods of semiconductor processing may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include depositing a silicon-containing material on the substrate. Subsequent a first period of time, the methods may include providing a germanium-containing precursor to the processing region of the semiconductor processing chamber. The methods may include thermally reacting the silicon-containing precursor and the germanium-containing precursor at a temperature greater than or about 400° C. The methods may include forming a silicon-and-germanium-containing layer on the substrate.Type: ApplicationFiled: May 19, 2021Publication date: November 24, 2022Applicant: Applied Materials, Inc.Inventors: Huiyuan Wang, Susmit Singha Roy, Abhijit Basu Mallick
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Publication number: 20220367270Abstract: Methods of forming and processing semiconductor devices which utilize a three-color process are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications. More particularly, certain embodiments relate to the formation of self-aligned gate contacts utilizing the formation of self-aligned growth pillars. The pillars lead to taller gate heights and increased margins against shorting defects.Type: ApplicationFiled: July 26, 2022Publication date: November 17, 2022Applicant: Micromaterials LLCInventors: Yuriy Shusterman, Madhur Sachan, Susmit Singha Roy, Regina Freed, Sanjay Natarajan
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Publication number: 20220359289Abstract: Apparatuses and methods to provide a fully self-aligned via are described. A first metallization layer comprises a set of first conductive lines extending along a first direction on a first insulating layer on a substrate, the set of first conductive lines recessed below a top portion of the first insulating layer. A capping layer is on the first insulating layer, and a second insulating layer is on the capping layer. A second metallization layer comprises a set of second conductive lines on the second insulating layer and on a third insulating layer above the first metallization layer. The set of second conductive lines extend along a second direction that crosses the first direction at an angle. At least one via is between the first metallization layer and the second metallization layer. The via is self-aligned along the second direction to one of the first conductive lines. The tapering angle of the via opening may be in a range of from about 60° to about 120°.Type: ApplicationFiled: July 26, 2022Publication date: November 10, 2022Applicant: Micromaterials LLCInventors: Regina Freed, Madhur Sachan, Susmit Singha Roy, Gabriela Alva, Ho-yung David Hwang, Uday Mitra, El Mehdi Bazizi, Angada Bangalore Sachid, He Ren, Sushant Mittal
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Patent number: 11462438Abstract: Methods of producing a self-aligned structure are described. The methods comprise forming a metal-containing film in a substrate feature and silicidizing the metal-containing film to form a self-aligned structure comprising metal silicide. In some embodiments, the rate of formation of the self-aligned structure is controlled. In some embodiments, the amount of volumetric expansion of the metal-containing film to form the self-aligned structure is controlled. Methods of forming self-aligned vias are also described.Type: GrantFiled: September 14, 2018Date of Patent: October 4, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Susmit Singha Roy, Srinivas Gandikota, Abhijit Basu Mallick, Amrita B. Mullick
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Patent number: 11437274Abstract: Apparatuses and methods to provide a fully self-aligned via are described. A first metallization layer comprises a set of first conductive lines extending along a first direction on a first insulating layer on a substrate, the set of first conductive lines recessed below a top portion of the first insulating layer. A capping layer is on the first insulating layer, and a second insulating layer is on the capping layer. A second metallization layer comprises a set of second conductive lines on the second insulating layer and on a third insulating layer above the first metallization layer. The set of second conductive lines extend along a second direction that crosses the first direction at an angle. At least one via is between the first metallization layer and the second metallization layer. The via is self-aligned along the second direction to one of the first conductive lines. The tapering angle of the via opening may be in a range of from about 60° to about 120°.Type: GrantFiled: September 14, 2020Date of Patent: September 6, 2022Assignee: Micromaterials LLCInventors: Regina Freed, Madhur Sachan, Susmit Singha Roy, Gabriela Alva, Ho-yung David Hwang, Uday Mitra, El Mehdi Bazizi, Angada Bangalore Sachid, He Ren, Sushant Mittal
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Patent number: 11437273Abstract: Methods of forming and processing semiconductor devices which utilize a three-color process are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications. More particularly, certain embodiments relate to the formation of self-aligned gate contacts utilizing the formation of self-aligned growth pillars. The pillars lead to taller gate heights and increased margins against shorting defects.Type: GrantFiled: February 24, 2020Date of Patent: September 6, 2022Assignee: Micromaterials LLCInventors: Yuriy Shusterman, Madhur Sachan, Susmit Singha Roy, Regina Freed, Sanjay Natarajan