Patents by Inventor Susumu Kasukabe

Susumu Kasukabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8816710
    Abstract: Provided is a micro contact element which is capable of coping with the miniaturization and greater complexity of substrates or boards, which is simplified due to a reduction in the number of components, and which creates sufficient contact pressure and stroke. Also provided is an inspection jig using this contact element. An inspection contact element having the contact pressure and amount of contraction required to carry out an inspection is formed by using notch parts respectively formed in two conductive cylindrical members having different outer and inner diameters so that the notch parts can function as elastic parts, and combining the two cylindrical members in such a way that the elastic parts are arranged in parallel or in series.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: August 26, 2014
    Assignee: Nidec-Read Corporation
    Inventors: Norihiro Ohta, Manabu Ohmayu, Susumu Kasukabe
  • Publication number: 20130033278
    Abstract: Provided is a micro contact element which is capable of coping with the miniaturization and greater complexity of substrates or boards, which is simplified due to a reduction in the number of components, and which creates sufficient contact pressure and stroke. Also provided is an inspection jig using this contact element. An inspection contact element having the contact pressure and amount of contraction required to carry out an inspection is formed by using notch parts respectively formed in two conductive cylindrical members having different outer and inner diameters so that the notch parts can function as elastic parts, and combining the two cylindrical members in such a way that the elastic parts are arranged in parallel or in series.
    Type: Application
    Filed: April 15, 2011
    Publication date: February 7, 2013
    Applicant: NIDEC-READ CORPORATION
    Inventors: Norihiro Ohta, Manabu Ohmayu, Susumu Kasukabe
  • Patent number: 8314624
    Abstract: A frame bonded and fixed to a back face of a probe sheet so as to surround a group of pyramid-shaped or truncated pyramid-shaped contact terminals collectively formed at a central region portion of the probe sheet on a probing side thereof is protruded from a multi-layered wiring board, and pressing force is imparted to the frame and a pressing piece at a central portion by a plurality of guide pins having spring property so as to tilt finely.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: November 20, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Susumu Kasukabe, Naoki Okamoto
  • Publication number: 20110169518
    Abstract: A frame bonded and fixed to a back face of a probe sheet so as to surround a group of pyramid-shaped or truncated pyramid-shaped contact terminals collectively formed at a central region portion of the probe sheet on a probing side thereof is protruded from a multi-layered wiring board, and pressing force is imparted to the frame and a pressing piece at a central portion by a plurality of guide pins having spring property so as to tilt finely.
    Type: Application
    Filed: March 25, 2011
    Publication date: July 14, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Susumu KASUKABE, Naoki OKAMOTO
  • Patent number: 7956627
    Abstract: A frame bonded and fixed to a back face of a probe sheet so as to surround a group of pyramid-shaped or truncated pyramid-shaped contact terminals collectively formed at a central region portion of the probe sheet on a probing side thereof is protruded from a multi-layered wiring board, and pressing force is imparted to the frame and a pressing piece at a central portion by a plurality of guide pins having spring property so as to tilt finely.
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: June 7, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Susumu Kasukabe, Naoki Okamoto
  • Publication number: 20110014727
    Abstract: In the highly accurate thin film probe sheet which is used for the contact to electrode pads disposed in high density with narrow pitches resulting from the increase in integration degree of semiconductor chips and for the inspection of semiconductor chips, a large spatial region in which a metal film selectively removable relative to terminal metal is formed in advance is formed in the peripheral region around minute contact terminals having sharp tips and disposed in high density with narrow pitches equivalent to those of the electrode pads. Thus, occurrence of damage in an inspection process is significantly reduced, and an inspection device simultaneously achieving the miniaturization and the durability can be provided.
    Type: Application
    Filed: September 16, 2010
    Publication date: January 20, 2011
    Inventors: Akira YABUSHITA, Yasunori Narizuka, Susumu Kasukabe, Terutaka Mori, Etsuko Takane, Akio Hasebe, Kenji Kawakami
  • Patent number: 7724006
    Abstract: A silicon substrate is used as a mold, and thin films such as metal films and polyimide films are sequentially stacked on the silicon substrate by using photolithography techniques, thereby forming a probe sheet having contact terminals having a pyramidal shape or a truncated pyramidal shape disposed at distal ends of cantilever beam structures. A fixing substrate is further fixed to the probe sheet, and then, the formed probe sheet is sequentially stacked and formed on the silicon substrate, the substrate is fixed, and the silicon substrate and predetermined polyimide films are removed by etching, thereby forming the group of contact terminals with the cantilever beam structures at a time.
    Type: Grant
    Filed: October 17, 2008
    Date of Patent: May 25, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Susumu Kasukabe, Yasunori Narizuka
  • Patent number: 7656174
    Abstract: A manufacturing method of a semiconductor device employing a semiconductor inspection apparatus to accurately inspect semiconductor elements while still in the wafer state, the semiconductor inspection apparatus including: a probe sheet 31 having contact terminals 7 which contact electrodes 3 of a wafer 1 and contact bumps 20b electrically connected to respective contact terminals 7; and a probe sheet 34 which is backed by a metal film 30b and having contact electrodes 34a which contact the contact bumps 20b of the probe sheet 31 and peripheral electrodes 27b electrically connected to the respective contact electrodes 34a, the wafer 1 is interposed between the probe sheet 34 and the supporting member 33 via the probe sheet 31 by reducing pressure through vacuuming, and the contact terminals 7 which have a pyramidal or truncated shape are contacted to the electrodes 3 of the wafer 1 at a desired atmospheric pressure, thereby performing the inspection.
    Type: Grant
    Filed: July 14, 2005
    Date of Patent: February 2, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Susumu Kasukabe, Yasunori Narizuka
  • Publication number: 20090212798
    Abstract: A silicon substrate is used as a mold, and thin films such as metal films and polyimide films are sequentially stacked on the silicon substrate by using photolithography techniques, thereby forming a probe sheet having contact terminals having a pyramidal shape or a truncated pyramidal shape disposed at distal ends of cantilever beam structures. A fixing substrate is further fixed to the probe sheet, and then, the formed probe sheet is sequentially stacked and formed on the silicon substrate, the substrate is fixed, and the silicon substrate and predetermined polyimide films are removed by etching, thereby forming the group of contact terminals with the cantilever beam structures at a time.
    Type: Application
    Filed: October 17, 2008
    Publication date: August 27, 2009
    Inventors: Susumu KASUKABE, Yasunori Narizuka
  • Publication number: 20090209053
    Abstract: To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multilayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multilayer film. A clamping member is provided on the frame to make the multilayer film project out to eliminate slack in the multilayer film. A contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member.
    Type: Application
    Filed: March 20, 2009
    Publication date: August 20, 2009
    Inventors: Susumu KASUKABE, Terutaka Mori, Akihiko Ariga, Hidetaka Shigi, Takayoshi Watanabe, Ryuji Kono
  • Patent number: 7541202
    Abstract: To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multiplayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multiplayer film. A clamping member is provided on the frame to make the multiplayer film project out to eliminate slack in the multiplayer film. A contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member.
    Type: Grant
    Filed: September 12, 2007
    Date of Patent: June 2, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Susumu Kasukabe, Terutaka Mori, Akihiko Ariga, Hidetaka Shigi, Takayoshi Watanabe, Ryuji Kono
  • Patent number: 7534629
    Abstract: By using a membrane probe formed by using a manufacturing technique for semiconductor integrated circuit devices, the yield of probing collectively performed on a plurality of chips is to be enhanced. A probe card is formed by using a plurality of pushers, each pusher being formed of a POGO pin insulator, POGO pins, an FPC connector, a membrane probe HMS, an impact easing sheet, an impact easing plate, a chip condenser YRS and so on, wherein one or two POGO pins press a plurality of metal films arranged like islands. One or more cuts are made into what matches the chip to be tested in the area of the membrane probe in a direction substantially parallel to the extending direction of wiring electrically connected to probes formed in the membrane probe.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: May 19, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Teruo Shoji, Akio Hasebe, Yoshinori Deguchi, Motoji Murakami, Masayoshi Okamoto, Yasunori Narizuka, Susumu Kasukabe
  • Publication number: 20090042323
    Abstract: A frame bonded and fixed to a back face of a probe sheet so as to surround a group of pyramid-shaped or truncated pyramid-shaped contact terminals collectively formed at a central region portion of the probe sheet on a probing side thereof is protruded from a multi-layered wiring board, and pressing force is imparted to the frame and a pressing piece at a central portion by a plurality of guide pins having spring property so as to tilt finely.
    Type: Application
    Filed: June 20, 2008
    Publication date: February 12, 2009
    Inventors: Susumu KASUKABE, Noaki OKAMOTO
  • Patent number: 7423439
    Abstract: In a prove card comprising: a probe sheet having a contact terminal contacting with an electrode provided on a wafer, a wiring led from the contact terminal, and an electrode electrically connected to the wiring; and a multilayered wiring substrate having an electrode electrically connected to the electrode of the probe sheet, wherein a contact between the contact terminal and the electrode of the wafer is established by one or more adhesion holder for pressing, from the backside of a terminal group of the terminal contacts, the terminal group via a press block with a spring to contact with the electrode pad. A device in which the probe sheet is attached to the adhesion holder and a plurality of chips are tested simultaneously by combining the adhesion holder.
    Type: Grant
    Filed: October 5, 2006
    Date of Patent: September 9, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Susumu Kasukabe, Teruo Shoji, Akio Hasebe, Yoshinori Deguchi, Yasunori Narizuka
  • Patent number: 7420380
    Abstract: A probe card, and a probe sheet used for the method of testing (producing) a semiconductor device using the probe card, include first contact terminals in electrical contact with the electrodes of a test object formed at a narrow pitch, wires connected with and led from the first contact terminals, and second contact terminals in electrical contact with the wires. The first and second contact terminals are formed using the etching holes of a crystalline member and lined with a metal sheet.
    Type: Grant
    Filed: July 2, 2004
    Date of Patent: September 2, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Susumu Kasukabe, Takeshi Yamamoto
  • Patent number: 7390732
    Abstract: A semiconductor device capable of facilitating high density mounting at low cost without causing any defective conduction at the time of connection to a substrate, a mounting structure thereof and a method of fabrication thereof, characterized in that pyramidal bump electrodes are bonded onto pad electrodes arranged on a semiconductor chip to form the semiconductor device.
    Type: Grant
    Filed: July 15, 1998
    Date of Patent: June 24, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Takayoshi Watanabe, Hidetaka Shigi, Susumu Kasukabe, Terutaka Mori
  • Patent number: 7351597
    Abstract: The fabrication of a semiconductor integrated circuit device involves testing using a pushing mechanism that is constructed by forming, over the upper surface of a thin film probe, a reinforcing material having a linear expansion coefficient (thermal expansion coefficient) almost equal to that of a wafer to be tested; forming a groove in the reinforcing material above a contact terminal; placing an elastomer in the groove so that a predetermined amount projects out of the groove; and disposing a pusher and another elastomer to sandwich the pusher between the elastomers. With the use of such a probe, it is possible to improve the throughput of wafer-level electrical testing of a semiconductor integrated circuit.
    Type: Grant
    Filed: May 18, 2007
    Date of Patent: April 1, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Yuji Wada, Susumu Kasukabe, Takehiko Hasebe, Yasunori Narizuka, Akira Yabushita, Terutaka Mori, Akio Hasebe, Yasuhiro Motoyama, Teruo Shoji, Masakazu Sueyoshi
  • Publication number: 20080029763
    Abstract: A probe sheet or a connecting sheet with good transmission characteristics and flexibility comprising contact terminals capable of contacting at a plurality of points and in high density, without applying damages on an electrode pad which is a contact subject is provided. Further, a high-speed transmission circuit capable of designing signal wirings with aligned impedance to have wide width even with a thin insulating film is achieved to provide a probe sheet or a connecting sheet with reduced loss of high-speed transmission signals. Moreover, the transmission circuit is applied to a probe card using a probe sheet, an inspecting method of (a method of manufacturing) a semiconductor device using the same, and a connecting sheet having an excellent high-frequency characteristic.
    Type: Application
    Filed: April 26, 2007
    Publication date: February 7, 2008
    Inventors: Susumu Kasukabe, Terutaka Mori, Yasunori Narizuka, Norio Chujo
  • Publication number: 20080009082
    Abstract: To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multiplayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multiplayer film. A clamping member is provided on the frame to make the multiplayer film project out to eliminate slack in the multiplayer film. A contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member.
    Type: Application
    Filed: September 12, 2007
    Publication date: January 10, 2008
    Inventors: Susumu Kasukabe, Terutaka Mori, Akihiko Ariga, Hidetaka Shigi, Takayoshi Watanabe, Ryuji Kono
  • Publication number: 20070279074
    Abstract: A full wafer inspection apparatus and a manufacturing method of a semiconductor device capable of collectively and precisely inspecting semiconductor elements formed on a wafer, while securing the positional accuracy of tip portions of contact terminals are provided.
    Type: Application
    Filed: July 14, 2005
    Publication date: December 6, 2007
    Inventors: Susumu Kasukabe, Yasunori Narizuka