Patents by Inventor Susumu Tsuruta

Susumu Tsuruta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9852099
    Abstract: A slave communication device is connected to a master communication device through a single bus, and transmits a data signal according to a synchronization signal transmitted from the master communication device. The slave communication device includes a current reduction unit that reduces a current flowing into the bus from the slave communication device at least in a period where the synchronization signal is transmitted from the master communication device.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: December 26, 2017
    Assignee: DENSO CORPORATION
    Inventors: Toshiaki Iwasaki, Susumu Tsuruta, Kouichi Maeda
  • Patent number: 9802560
    Abstract: An electronic circuit includes a regulator circuit including at least one regulator configured to supply a predetermined voltage by receiving a power supply from a main power source circuit, a functional circuit configured to operate on the voltage supplied from the regulator and perform a predetermined function, and a monitor circuit connected to at least one of the regulators and configured to monitor operation mode information inputted to the regulator. When detecting that the operation mode information contains sleep transition information to make a transition from a normal mode as a normal operation state to a sleep mode as an operation state where power consumption is smaller than that in the normal mode, the monitor circuit outputs a voltage output maintaining signal to the regulator connected to the monitor circuit to supply the voltage capable of causing the functional circuit to operate in the normal mode.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: October 31, 2017
    Assignee: DENSO CORPORATION
    Inventors: Nobuo Umegaki, Susumu Tsuruta
  • Publication number: 20150331819
    Abstract: A slave communication device is connected to a master communication device through a single bus, and transmits a data signal according to a synchronization signal transmitted from the master communication device. The slave communication device includes a current reduction unit that reduces a current flowing into the bus from the slave communication device at least in a period where the synchronization signal is transmitted from the master communication device.
    Type: Application
    Filed: May 14, 2015
    Publication date: November 19, 2015
    Inventors: Toshiaki IWASAKI, Susumu TSURUTA, Kouichi MAEDA
  • Publication number: 20150291110
    Abstract: An electronic circuit includes a regulator circuit including at least one regulator configured to supply a predetermined voltage by receiving a power supply from a main power source circuit, a functional circuit configured to operate on the voltage supplied from the regulator and perform a predetermined function, and a monitor circuit connected to at least one of the regulators and configured to monitor operation mode information inputted to the regulator. When detecting that the operation mode information contains sleep transition information to make a transition from a normal mode as a normal operation state to a sleep mode as an operation state where power consumption is smaller than that in the normal mode, the monitor circuit outputs a voltage output maintaining signal to the regulator connected to the monitor circuit to supply the voltage capable of causing the functional circuit to operate in the normal mode.
    Type: Application
    Filed: October 24, 2013
    Publication date: October 15, 2015
    Inventors: Nobuo Umegaki, Susumu Tsuruta
  • Patent number: 8924606
    Abstract: It is provided a storage system for inputting and outputting data in accordance with a request from a host computer, comprising: at least one processor for processing data requested to be input or output; a plurality of transfer controllers for transferring data between memories in the storage system; and at least one transfer sequencer for requesting a data transfer to the plurality of transfer controllers in accordance with an instruction from the processor. The processor transmits a series of data transfer requests to the at least one transfer sequencer. The at least one transfer sequencer requests a data transfer to each of the plurality of transfer controllers based on the series of data transfer requests. The each transfer controller transfers data between the memories in accordance with an instruction from the at least one transfer sequencer.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: December 30, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Koji Akiyama, Susumu Tsuruta, Hideaki Fukuda, Hiroshi Shimmura, Shoji Kato
  • Patent number: 8694698
    Abstract: According to a prior art data transfer method of a storage subsystem, when competition of data transfer accesses occurs, a free access destination port is allocated uniformly without determining the access type or the access state of the access destination, so that the performance of the device is not enhanced. The present invention solves the problem by selecting a data transfer access for completing data transfer with priority based on the access type or the remaining transfer data quantity of competing data transfer accesses, or by changing the access destination of an access standby data transfer access, thereby performing data transfer efficiently.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: April 8, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Makio Mizuno, Masanori Takada, Tomohiro Yoshihara, Susumu Tsuruta
  • Publication number: 20130275630
    Abstract: According to a prior art data transfer method of a storage subsystem, when competition of data transfer accesses occurs, a free access destination port is allocated uniformly without determining the access type or the access state of the access destination, so that the performance of the device is not enhanced. The present invention solves the problem by selecting a data transfer access for completing data transfer with priority based on the access type or the remaining transfer data quantity of competing data transfer accesses, or by changing the access destination of an access standby data transfer access, thereby performing data transfer efficiently.
    Type: Application
    Filed: April 12, 2012
    Publication date: October 17, 2013
    Inventors: Makio Mizuno, Masanori Takada, Tomohiro Yoshihara, Susumu Tsuruta
  • Publication number: 20130232284
    Abstract: It is provided a storage system for inputting and outputting data in accordance with a request from a host computer, comprising: at least one processor for processing data requested to be input or output; a plurality of transfer controllers for transferring data between memories in the storage system; and at least one transfer sequencer for requesting a data transfer to the plurality of transfer controllers in accordance with an instruction from the processor. The processor transmits a series of data transfer requests to the at least one transfer sequencer. The at least one transfer sequencer requests a data transfer to each of the plurality of transfer controllers based on the series of data transfer requests. The each transfer controller transfers data between the memories in accordance with an instruction from the at least one transfer sequencer.
    Type: Application
    Filed: March 2, 2012
    Publication date: September 5, 2013
    Inventors: Koji Akiyama, Susumu Tsuruta, Hideaki Fukuda, Hiroshi Shimmura, Shoji Kato
  • Publication number: 20120221809
    Abstract: Comprises a memory control unit which transmits and receives data to and from respective interface control units in accordance with access requests and also controls access to the memory and a buffer which temporarily stores data smaller than 64 B, wherein the memory control unit, during access to the memory, if the processing data to be processed is 64 B, accesses the memory by using the processing data or, if the processing data is data smaller than 64 B, stores the data smaller than 64 B in the buffer, subsequently, if the address of the new processing data which became the processing data is sequential to the address of the data smaller than 64 B stored in the buffer, combines the new processing data and the data of the buffer and, on condition that the combined processing data is 64 B data, writes the combined processing data in the memory.
    Type: Application
    Filed: February 28, 2011
    Publication date: August 30, 2012
    Inventors: Takao Yoshikawa, Susumu Tsuruta, Tetsuhiro Okabe, Nobuharu Shibuya
  • Patent number: 8161221
    Abstract: It is an object to prevent a processing speed of the storage system provided with a function for detecting a write completion of data from being reduced. A controller module is provided with at least one processor module, at least one storage resource, and at least one transfer control module connected to the processor module and the storage resource. The transfer control module is provided with a receiver and a transmitter. The receiver receives a write packet from the processor module, includes a specific code in the write packet, and then transmits the write packet. In the case in which the transmitter receives a write packet and the received write packet includes the specific code, the transmitter writes targeted data in the write packet to the storage resource to be written, generates a response packet that is a response indicating a completion of a write, and transmits the generated response packet.
    Type: Grant
    Filed: November 25, 2008
    Date of Patent: April 17, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Suguru Shimotaya, Susumu Tsuruta, Daisuke Isobe
  • Patent number: 7996712
    Abstract: A data transfer controller of the present invention can determine whether or not data has been correctly stored in a cache memory even when the data is not transferred to the cache memory in sequential order. Data inputted from a host is transferred to and stored in a prescribed area of the cache memory. First check data is created and stored for each block. A data consistency determination module reads out the data from the cache memory subsequent to the end of a data write, and creates second check data anew. By comparing the second check data against the first check data, it can be determined whether or not the data has been stored normally in the cache memory. The data consistency determination module can also determine the consistency of the data on the basis of the data address written to the cache memory.
    Type: Grant
    Filed: April 21, 2008
    Date of Patent: August 9, 2011
    Assignee: Hitachi, Ltd.
    Inventor: Susumu Tsuruta
  • Publication number: 20110153884
    Abstract: It is an object to prevent a processing speed of the storage system provided with a function for detecting a write completion of data from being reduced. A controller module is provided with at least one processor module, at least one storage resource, and at least one transfer control module connected to the processor module and the storage resource. The transfer control module is provided with a receiver and a transmitter. The receiver receives a write packet from the processor module, includes a specific code in the write packet, and then transmits the write packet. In the case in which the transmitter receives a write packet and the received write packet includes the specific code, the transmitter writes targeted data in the write packet to the storage resource to be written, generates a response packet that is a response indicating a completion of a write, and transmits the generated response packet.
    Type: Application
    Filed: November 25, 2008
    Publication date: June 23, 2011
    Applicant: Hitachi Ltd.
    Inventors: Suguru Shimotaya, Susumu Tsuruta, Daisuke Isobe
  • Publication number: 20110154165
    Abstract: A storage apparatus includes: a host control unit for sending/receiving data to/from a host server; a drive control unit for sending/receiving the data to/from a storage device; a cache memory for temporarily storing the data sent and received between the host control unit and the drive control unit; a switch for switching between a transfer source and a transfer destination when transferring the data by selecting the transfer source and the transfer destination from among the host control unit, the cache memory, and the drive control unit; and a controller for controlling the host control unit, the drive control unit, and the switch; wherein processing for generating an error check code for the data and error check processing using the error check code are executed by the switch or are distributed among and executed by the host control unit, the drive control unit, the switch, and the controller.
    Type: Application
    Filed: June 4, 2009
    Publication date: June 23, 2011
    Inventors: Zaki Primadani, Xiaoming Jiang, Susumu Tsuruta
  • Patent number: 7953904
    Abstract: A storage control apparatus capable of reducing a power consumption in network port units, including a host communication control unit 10 which includes a plurality of network ports 18 and which controls communications with a host computer 2 that is connectable through the network ports, a storage-device communication control unit 16 which controls communications with a plurality of storage devices, a plurality of DMA portions 111 by which data to be transmitted/received between the host computer and the storage devices are transferred between the host communication control unit 10 and the storage-device communication control unit 16, a plurality of cache memories 12 in which the data to be transferred by the DMA portions 111 are temporarily stored, and a power saving control portion 110 which stops the DMA portion 111 and the cache memory 12 that are previously associated with one network port, on the basis of a connection situation of the pertinent network port with the host computer and a data rate to be i
    Type: Grant
    Filed: October 17, 2008
    Date of Patent: May 31, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Masateru Hemmi, Susumu Tsuruta, Daisuke Isobe
  • Publication number: 20100057948
    Abstract: A storage control apparatus capable of reducing a power consumption in network port units, including a host communication control unit 10 which includes a plurality of network ports 18 and which controls communications with a host computer 2 that is connectable through the network ports, a storage-device communication control unit 16 which controls communications with a plurality of storage devices, a plurality of DMA portions 111 by which data to be transmitted/received between the host computer and the storage devices are transferred between the host communication control unit 10 and the storage-device communication control unit 16, a plurality of cache memories 12 in which the data to be transferred by the DMA portions 111 are temporarily stored, and a power saving control portion 110 which stops the DMA portion 111 and the cache memory 12 that are previously associated with one network port, on the basis of a connection situation of the pertinent network port with the host computer and a data rate to be i
    Type: Application
    Filed: October 17, 2008
    Publication date: March 4, 2010
    Inventors: Masateru Hemmi, Susumu Tsuruta, Daisuke Isobe
  • Publication number: 20090210634
    Abstract: A data transfer controller of the present invention can determine whether or not data has been correctly stored in a cache memory even when the data is not transferred to the cache memory in sequential order. Data inputted from a host is transferred to and stored in a prescribed area of the cache memory. First check data is created and stored for each block. A data consistency determination module reads out the data from the cache memory subsequent to the end of a data write, and creates second check data anew. By comparing the second check data against the first check data, it can be determined whether or not the data has been stored normally in the cache memory. The data consistency determination module can also determine the consistency of the data on the basis of the data address written to the cache memory.
    Type: Application
    Filed: April 21, 2008
    Publication date: August 20, 2009
    Inventor: Susumu Tsuruta
  • Patent number: 7526592
    Abstract: An interrupt control system is provided where a signal-line-based interrupt system can be incorporated into interrupt control using MSIs (Message Signal Interrupts). The interrupt control system includes a first PCI interface, a second PCI interface, a PCI bridge serving as a bridge between the first PCI interface and the second PCI interface, and a control circuit for controlling an interrupt signal. The PCI bridge recognizes a message signal interrupt issued from the first PCI interface to the second PCI interface and transfers the message signal interrupt to the control circuit, and the control circuit is provided with an interrupt conversion unit for converting the message signal interrupt into an interrupt signal and outputting it via a signal line.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: April 28, 2009
    Assignee: Hitachi, Ltd.
    Inventor: Susumu Tsuruta
  • Publication number: 20080082713
    Abstract: An interrupt control system is provided where a signal-line-based interrupt system can be incorporated into interrupt control using MSIs (Message Signal Interrupts). The interrupt control system includes a first PCI interface 40, a second PCI interface 43, a PCI bridge 44 serving as a bridge between the first PCI interface and the second PCI interface, and a control circuit 54 for controlling an interrupt signal. The PCI bridge recognizes a message signal interrupt issued from the first PCI interface to the second PCI interface and transfers the message signal interrupt to the control circuit, and the control circuit is provided with an interrupt conversion unit for converting the message signal interrupt into an interrupt signal and outputting it via a signal line.
    Type: Application
    Filed: November 28, 2006
    Publication date: April 3, 2008
    Inventor: Susumu Tsuruta
  • Patent number: 7216250
    Abstract: The present invention relates to a clock control circuit apparatus including a first oscillation circuit for generating a first clock signal and a second oscillation circuit for generating a second clock signal and capable of, when the two clock signals are put to use, improving the reliability of oscillation operations thereof. In the clock control circuit apparatus, a sub-clock correction unit corrects an oscillation frequency of a sub-clock signal on the basis of a main clock signal, while a main clock monitoring unit monitors an oscillation state of the main clock signal on the basis of the sub-clock signal.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: May 8, 2007
    Assignee: DENSO Corporation
    Inventors: Toshihiko Matsuoka, Yoshinori Teshima, Shinichi Noda, Susumu Tsuruta, Hiroshi Fujii, Hideaki Ishihara
  • Publication number: 20060059302
    Abstract: There is a technique for a disk array subsystem which can reduce the number of LSIs required per one channel and mount more channels on a package, in a package of a channel control unit. In the disk array subsystem, a channel control unit receiving a data input/output request from an external unit has: a plurality of link control LSIs establishing communication with the external unit; a plurality of processors (MP) processing the data input/output command from the external unit; and a channel control LSI having a bridge control unit for changing a plurality of buses respectively connected to the link control LSIs and processors, connecting the bus connected to the link control LSI and the bus connected to the processor by the bridge control unit, and transferring the data between the link control LSI and the cache memory in accordance with the processor.
    Type: Application
    Filed: November 9, 2004
    Publication date: March 16, 2006
    Inventor: Susumu Tsuruta