Abstract: Power consumption due to failed automatic calibration is suppressed. An electronic watch is provided with a magnetic sensor, a processor for performing calibration of the magnetic sensor and controlling two or more function modes, and an acceleration sensor for sensing movement of a user. The processor determines whether a state of movement sensed by the acceleration sensor is a calibratable state in which calibration of the magnetic sensor can be performed, performs discrimination of a function mode being executed among the two or more function modes, and performs the calibration of the magnetic sensor when (i) the state of movement sensed by the acceleration sensor is the calibratable state and (ii) the function mode is not a non-default mode, the non-default mode being a function mode executed in accordance with an operation by the user.

Abstract: Display data of pixels is updated at different timings. A scan line is connected to a first pixel and a second pixel, a first wiring is connected to the first pixel, and a second wiring is connected to the second pixel. In a first period, a signal for selecting the first pixel and the second pixel is supplied to the scan line. Setting data for setting a state where the display data of the first pixel is updated is supplied to the first wiring, and setting data for setting a state where the display data of the second pixel is updated is supplied to the second wiring. In a second period, a signal for selecting the first pixel and the second pixel is supplied to the scan line. Setting data for setting a state where the display data of the first pixel is not updated is supplied to the first wiring, and the setting data for setting the state where the display data of the second pixel is updated is supplied to the second wiring.

Abstract: An image pickup apparatus includes: an image pickup device including a plurality of pixels generating an image pickup signal corresponding to a light reception amount; a universal cable for transmitting electric power to the image pickup device; an AC-voltage-pulse-signal generation circuit provided on a proximal end side of the universal cable and generating an AC voltage pulse signal obtained by converting a positive voltage level and a negative voltage level of an inputted pulse signal into a predetermined positive voltage level and a predetermined negative voltage level, respectively, and outputting the AC voltage pulse signal to the universal cable; and a voltage adjustment circuit provided on a distal end side of the universal cable and converting the predetermined positive voltage level and the predetermined negative voltage level of the AC voltage pulse signal transmitted from the universal cable into a DC voltage level and output a DC voltage pulse signal.

Abstract: Power consumption due to failed automatic calibration is suppressed. An electronic watch is provided with a magnetic sensor, a processor for performing calibration of the magnetic sensor and controlling two or more function modes, and an acceleration sensor for sensing movement of a user. The processor determines whether a state of movement sensed by the acceleration sensor is a calibratable state in which calibration of the magnetic sensor can be performed, performs discrimination of a function mode being executed among the two or more function modes, and performs the calibration of the magnetic sensor when (i) the state of movement sensed by the acceleration sensor is the calibratable state and (ii) the function mode is not a non-default mode, the non-default mode being a function mode executed in accordance with an operation by the user.

Abstract: An imaging device includes: a pulse-signal superimposing circuit configured to superimpose a first pulse signal generated by a pulse-signal generator on a voltage; a separating circuit that is disposed between a light receiver and a transmission cable, the separating circuit being configured to separate an offset voltage and a pulse voltage from the voltage transmitted through the transmission cable and output the offset voltage to the light receiver; a pulse-signal detector configured to detect the first pulse signal superimposed on the transmission cable; a pulse-signal converting circuit configured to convert a frequency of the first pulse signal detected by the pulse-signal detector into a frequency of a second pulse signal used to generate a synchronization signal for driving the light receiver; and a timing generator configured to generate the synchronization signal based on the second pulse signal obtained after conversion by the pulse-signal converting circuit.

Abstract: An image sensor includes: photoelectric conversion elements configured to receive light and accumulate a charge corresponding to an amount of received light; an imaging signal generating unit that converts the charge accumulated in each photoelectric conversion element into a voltage to generate an imaging signal; and a reference signal generating unit that generates a reference signal having a fluctuation component with a same phase as the imaging signal. The imaging signal generating unit includes: a conversion circuit that converts the charge accumulated in each photoelectric conversion element into the imaging signal; a noise eliminating circuit that eliminates a noise component included in the imaging signal; and an output circuit that outputs the imaging signal from the conversion circuit. The reference signal generating unit includes a circuit having a same structure as that of at least one of the conversion circuit, the noise eliminating circuit, and the output circuit.

Abstract: An image sensor includes: a plurality of pixels arranged in a two-dimensional matrix form and configured to receive light from outside and generate and output an imaging signal depending on an amount of the received light; a transfer unit configured to transfer the imaging signal output from each of the pixels; a sample-and-hold unit configured to hold and output the imaging signal transferred from the transfer unit; a reference voltage generation unit configured to generate and output a reference voltage; an amplifier connected to the sample-and-hold unit and to the reference voltage generation unit and configured to amplify and output the imaging signal input from the sample-and-hold unit using the reference voltage as a reference; and a control unit configured to control the reference voltage to be input to the amplifier during at least one of a horizontal blanking period and a video signal period of the imaging signal.

Abstract: An imaging element includes: a plurality of pixels configured to receive light from outside and generate and output an imaging signal depending on an amount of the light received; a first transfer line connected to the pixel; a second transfer line; a column selection switch configured to select one pixel column and output the imaging signal to the second transfer line; a column source follower including a gate to which the imaging signal transferred by the first transfer line is input, a drain end being connected to a power supply voltage, and a source end being connected to the column selection switch; a constant current source configured to drive the column source follower and read out the imaging signal to the second transfer line; and a current generating unit configured to flow a predetermined current to the source end side of the column source follower.

Abstract: An image sensor includes: a plurality of pixels arranged in a two-dimensional matrix form and configured to receive light from outside and generate and output an imaging signal depending on an amount of the received light; a transfer unit configured to transfer the imaging signal output from each of the pixels; a sample-and-hold unit configured to hold and output the imaging signal transferred from the transfer unit; a reference voltage generation unit configured to generate and output a reference voltage; an amplifier connected to the sample-and-hold unit and to the reference voltage generation unit and configured to amplify and output the imaging signal input from the sample-and-hold unit using the reference voltage as a reference; and a control unit configured to control the reference voltage to be input to the amplifier during at least one of a horizontal blanking period and a video signal period of the imaging signal.

Abstract: An image sensor includes: photoelectric conversion elements configured to receive light and accumulate a charge corresponding to an amount of received light; an imaging signal generating unit that converts the charge accumulated in each photoelectric conversion element into a voltage to generate an imaging signal; and a reference signal generating unit that generates a reference signal having a fluctuation component with a same phase as the imaging signal. The imaging signal generating unit includes: a conversion circuit that converts the charge accumulated in each photoelectric conversion element into the imaging signal; a noise eliminating circuit that eliminates a noise component included in the imaging signal; and an output circuit that outputs the imaging signal from the conversion circuit. The reference signal generating unit includes a circuit having a same structure as that of at least one of the conversion circuit, the noise eliminating circuit, and the output circuit.

Abstract: A solid-state imaging apparatus includes a plurality of photoelectric conversion sections configured to generate a signal charge according to an amount of an incident light and disposed in a matrix, a first accumulation section configured to accumulate the signal charge, a first transfer section configured to transfer the signal charge from the photoelectric conversion sections to the first accumulation section, a second accumulation section configured to accumulate the signal charge accumulated in the first accumulation section, a second transfer section configured to transfer the signal charge accumulated in the first accumulation section to the second accumulation section, a reset section configured to reset the signal charge accumulated in the second accumulation section, an output section configured to output a signal according to the signal charge accumulated in the second accumulation section, and first and second control sections configured to control each section for every row or column.

Abstract: According to one embodiment, a memory controller includes a bank controller including a queuing part queuing commands associated with a bank and having a first flag associated with each of the commands, the bank controller executing the commands in order, a data controller transferring write data to the bank when a particular command to be executed among the commands is a write command associated with one of physical addresses in the bank, and a parity controller generating parity data for restoring the write data based on a value of a first flag associated with the particular command, before execution of the particular command is completed.

Abstract: According to one embodiment, there is provided a device including a non-volatile memory and a controller. The non-volatile memory includes a memory cell array and an internal buffer. The controller is configured to, after failure of an error correcting process of first data read from the memory cell array, store second data generated from the first data in the internal buffer and read the stored second data from the internal buffer to perform the error correcting process.

Abstract: A solid-state imaging apparatus includes a pixel unit which has a plurality of pixels disposed in a two-dimensional matrix shape, wherein each of the pixels that a photoelectrical conversion element which generates a photoelectrical conversion signal corresponding to an amount of incident light disposed on a first substrate, and which outputs a photoelectrical conversion signal generated by each of the pixels to each row as a pixel signal, and an analog-to-digital converter which is disposed on every one or more columns of the pixel unit and generates a digital signal by digitizing a phase state of a multi-phase clock including clock signals of a plurality of phases different from each other at predetermined fixed intervals according to the pixel signal. Each of first and second circuit configuration units whose circuit scales are determined according to the multi-phase clock is disposed on a different substrate of a first or second substrate.

Abstract: A switching circuit comprising: a semiconductor layer including a source region, a drain region, and a channel region; a gate electrode disposed to be opposite to the channel region; a source wiring formed of a first material having higher conductivity than the semiconductor layer; a drain wiring formed of a second material having higher conductivity than the semiconductor layer; and a decoupling wiring formed of a third material having higher conductivity than the semiconductor layer, wherein the source region and the drain region are in a conductive state in a first period according to a voltage of the gate electrode, and the source region and the drain region are in a non-conductive state in a second period different from the first period, and wherein a voltage of the decoupling wiring is constant in at least a partial period of the second period.

Abstract: According to an embodiment, a storage device includes: a semiconductor memory that includes a multilevel memory cell, stores a first code word and a second code word, and in which a plurality of memory cells connected to one word line can store a plurality of pages; and a controller. The controller performs error correction processing of the first code word read out from one page among the plurality of pages of the semiconductor memory, and the second code word written in a page other than the page corresponding to the first code word among the plurality of pages, re-reads the first code word when the first code word is uncorrectable and the second code word was able to be corrected by the error correction processing, and determines a bit value of the first code word using a re-read result and the second code word after error correction.

Abstract: An imaging element includes: a plurality of pixels configured to receive light from outside and generate and output an imaging signal depending on an amount of the light received; a first transfer line connected to the pixel; a second transfer line; a column selection switch configured to select one pixel column and output the imaging signal to the second transfer line; a column source follower including a gate to which the imaging signal transferred by the first transfer line is input, a drain end being connected to a power supply voltage, and a source end being connected to the column selection switch; a constant current source configured to drive the column source follower and read out the imaging signal to the second transfer line; and a current generating unit configured to flow a predetermined current to the source end side of the column source follower.

Abstract: In an A/D conversion circuit and a solid-state imaging device, a latch circuit is in a disable state until a first timing at which an output signal of a comparison unit has been inverted, and is in an enable state until a second timing at which a delay time of the inversion delay circuit has passed from the first timing. The latch circuit is in the enable state until the second timing according to comparison start in the comparison unit. The latch circuit latches an output signal of a delay unit at the second timing. A determination unit determines whether the latch circuit accurately latches the output signal of the delay unit, and outputs a signal indicating a determination result to a delay controller. The delay controller controls the delay time of the inversion delay circuit based on the determination result.

Abstract: A solid-state imaging apparatus includes a plurality of photoelectric conversion sections configured to generate a signal charge according to an amount of an incident light and disposed in a matrix, a first accumulation section configured to accumulate the signal charge, a first transfer section configured to transfer the signal charge from the photoelectric conversion sections to the first accumulation section, a second accumulation section configured to accumulate the signal charge accumulated in the first accumulation section, a second transfer section configured to transfer the signal charge accumulated in the first accumulation section to the second accumulation section, a reset section configured to reset the signal charge accumulated in the second accumulation section, an output section configured to output a signal according to the signal charge accumulated in the second accumulation section, and first and second control sections configured to control each section for every row or column.

Abstract: An AD conversion circuit includes: a comparison unit that receives an analog signal and a reference signal, compares voltages of the signals, and outputs a first comparison signal; a signal generation unit that outputs a second comparison signal for switching a logic state, and outputs a third comparison signal that is a result of a logic operation on the first comparison signal and the second comparison signal; a control unit that outputs an enable signal; a clock generation unit that outputs first to nth clock signals having different phases; a latch unit that includes first to nth latch units, each of the first to nth latch units including an input terminal, a first control terminal, a second control terminal, and an output terminal, and latches a logic state of the one of the first to nth clock signals; and a count unit that performs a count operation.