Patents by Inventor Susumu Yoshikawa

Susumu Yoshikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240107685
    Abstract: A printed wiring board includes a first conductor layer, a resin insulating layer having an opening, a second conductor layer including a seed layer and an electrolytic plating layer formed on the seed layer, and a via conductor including the seed layer and the electrolytic plating layer and connecting the first conductor and second conductor layers. The seed layer has a first portion on the surface of the insulating layer, a second portion on an inner wall surface in the opening of the insulating layer, and a third portion on a portion of the first conductor layer exposed by the opening of the insulating layer such that the first portion is thicker than the second portion and the third portion, the second portion has a first film and a second film electrically connected to the first film, and a portion of the first film is formed on the second film.
    Type: Application
    Filed: September 27, 2023
    Publication date: March 28, 2024
    Applicant: IBIDEN CO., LTD.
    Inventors: Susumu KAGOHASHI, Jun SAKAI, Kyohei YOSHIKAWA, Takuya INISHI
  • Publication number: 20240098892
    Abstract: A printed wiring board includes a first conductor layer, a resin insulating layer laminated on the first conductor layer and including resin material and inorganic particles, a second conductor layer formed on a first surface of the insulating layer such that the first conductor layer is facing a second surface of the insulating layer, and a via conductor formed in an opening extending through the insulating layer and connecting the first and second conductor layers. The insulating layer is formed such that the inorganic particles include first inorganic particles partially embedded in the resin and second inorganic particles completely embedded in the resin, the first inorganic particles have first portions protruding from the resin and second portions embedded in the resin respectively, and the first surface of the resin insulating layer includes a surface of the resin and surfaces of the first portions exposed from the surface of the resin.
    Type: Application
    Filed: April 27, 2023
    Publication date: March 21, 2024
    Applicant: IBIDEN CO., LTD.
    Inventors: Susumu KAGOHASHI, Jun SAKAI, Kyohei YOSHIKAWA
  • Publication number: 20190356014
    Abstract: The lithium ion secondary battery includes an electrode body and a nonaqueous electrolyte liquid. The negative electrode active material in the negative electrode includes a materials S including Si. Assuming that a total of all negative electrode active materials included in the negative electrode is 100 mass %, a content of the material S is higher than 5 mass %. The nonaqueous electrolyte liquid comprises propylene carbonate and a chain carbonate as a solvent. A volume content of the propylene carbonate in the solvent is 10 to 50 volume %. The positive electrode comprises a positive electrode composition layer comprising a metal oxide comprising Li and a metal M except for Li as a positive electrode active material provided on at least one surface of a positive electrode current collector. The lithium ion secondary battery has an upper limit voltage in charge is 4.35 V of more.
    Type: Application
    Filed: August 28, 2017
    Publication date: November 21, 2019
    Applicant: MAXELL HOLDINGS, LTD.
    Inventors: Hiroshi Abe, Susumu Yoshikawa, Tomohito Sekiya
  • Patent number: 9819018
    Abstract: There is provided a lithium ion secondary battery with a high capacity and having excellent cycle characteristics. The lithium ion secondary battery, including a positive electrode, a negative electrode, a separator and a nonaqueous electrolyte liquid. Here, the positive electrode comprises a positive electrode material in which a surface of particles of a positive electrode active material is coated with an Al-containing oxide. The Al-containing oxide has an average coating thickness of 5 to 50 nm. The positive electrode active material contained in the positive electrode material comprises a lithium cobalt oxide comprising Co and at least one kind of an element M1 selected from the group consisting of Mg, Zr, Ni, Mn, Ti and Al. The negative electrode comprises a material S including SiOx (0.5?x?1.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: November 14, 2017
    Assignee: HITACHI MAXELL, LTD.
    Inventors: Tomohito Sekiya, Hiroshi Abe, Akira Inaba, Susumu Yoshikawa, Yuji Hashimoto, Seiji Ishizawa, Toshihiro Abe
  • Publication number: 20160351900
    Abstract: There is provided a lithium ion secondary battery with a high capacity and having excellent cycle characteristics. The lithium ion secondary battery, including a positive electrode, a negative electrode, a separator and a nonaqueous electrolyte liquid. Here, the positive electrode comprises a positive electrode material in which a surface of particles of a positive electrode active material is coated with an Al-containing oxide. The Al-containing oxide has an average coating thickness of 5 to 50 nm. The positive electrode active material contained in the positive electrode material comprises a lithium cobalt oxide comprising Co and at least one kind of an element M1 selected from the group consisting of Mg, Zr, Ni, Mn, Ti and Al. The negative electrode comprises a material S including SiOx (0.5?x?1.
    Type: Application
    Filed: May 31, 2016
    Publication date: December 1, 2016
    Applicant: HITACHI MAXELL, LTD.
    Inventors: Tomohito Sekiya, Hirosi Abe, Akira Inaba, Susumu Yoshikawa, Yuji Hashimoto, Seiji Ishizawa, Toshihiro Abe
  • Patent number: 9287506
    Abstract: The present invention provides a fullerene derivative having an electron donating group adjacent to the fullerene nucleus, represented by formula (I) which exhibits a high LUMO energy and a high open circuit voltage based thereon and which is highly compatible with polymers and excellent in charge mobility and charge separation ability: wherein the encircled FL represents fullerene C60 or C70, Donor-Sub represents a substituent having at least one electron donating substituent atom located at a position apart from the fullerene nucleus by two bonds, R is hydrogen, Donor-Sub, an alkyl, cycloalkyl, alkoxy, alkoxy-substituted alkyl, alkoxy-substituted alkoxy, alkylthio-substituted alkoxy, alkylthio, alkylthio-substituted alkylthio, or alkoxy-substituted alkylthio group, having a total carbon atoms of 1 or more and 20 or fewer, or a benzyl or phenyl group, and n is an integer of 1 to 10.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: March 15, 2016
    Assignees: JX Nippon Oil & Energy Corporation, Osaka Municipal Technical Research Institute, Kyoto University
    Inventors: Toshinobu Ohno, Yuko Takao, Kazuyuki Moriwaki, Fukashi Matsumoto, Takatoshi Ito, Toshiyuki Iwai, Susumu Yoshikawa, Takashi Sagawa, Soichi Uchida, Satoru Ikeda
  • Publication number: 20140014882
    Abstract: The present invention provides a fullerene derivative having an electron donating group adjacent to the fullerene nucleus, represented by formula (I) which exhibits a high LUMO energy and a high open circuit voltage based thereon and which is highly compatible with polymers and excellent in charge mobility and charge separation ability: wherein the encircled FL represents fullerene C60 or C70, Donor-Sub represents a substituent having at least one electron donating substituent atom located at a position apart from the fullerene nucleus by two bonds, R is hydrogen, Donor-Sub, an alkyl, cycloalkyl, alkoxy, alkoxy-substituted alkyl, alkoxy-substituted alkoxy, alkylthio-substituted alkoxy, alkylthio, alkylthio-substituted alkylthio, or alkoxy-substituted alkylthio group, having a total carbon atoms of 1 or more and 20 or fewer, or a benzyl or phenyl group, and n is an integer of 1 to 10.
    Type: Application
    Filed: January 17, 2012
    Publication date: January 16, 2014
    Applicants: JX NIPPON OIL & ENERGY CORPORATION, KYOTO UNIVERSITY, OSAKA MUNICIPAL TECHNICAL RESEARCH INSTITUTE
    Inventors: Toshinobu Ohno, Yuko Takao, Kazuyuki Moriwaki, Fukashi Matsumoto, Takatoshi Ito, Toshiyuki Iwai, Susumu Yoshikawa, Takashi Sagawa, Soichi Uchida, Satoru Ikeda
  • Patent number: 8207522
    Abstract: A composite of a base and an array of needle-like crystals formed on a surface of the base is provided, in which the base side and the opposite side to the base with respect to the array can be isolated in a satisfactory manner. A composite 10 contains a transparent electrode 2 serving as the base and an array 4 of needle-like crystals 3 formed thereon. The needle-like crystals 3 are made of, for example, zinc oxide. The array 4 includes a first region R1 on the transparent electrode 2 side and a second region R2 on the opposite side to the transparent electrode 2 with respect to the first region R1. A proportion of the cross section of the needle-like crystals 3 in a plane parallel to the surface of the transparent electrode 2 is lower in the second region R2 than in the first region R1, and the surface of the transparent electrode 2 is substantially covered with the needle-like crystals 3 in the first region R1.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: June 26, 2012
    Assignees: Kyocera Corporation
    Inventors: Junji Aranami, Susumu Yoshikawa
  • Patent number: 8104678
    Abstract: A payment approval system and a method for approving a payment for credit cards are provided for providing efficient processing while maintaining accuracy in detection of fraud usage of credit cards with an IC chip. Fraud parameters obtained by modeling a pattern of fraud usage is stored in the IC chip equipped in the IC credit card to use for payment approval to achieve improved reliability of offline approval. When offline approval process finds a possibility of fraud usage, online approval for more detailed statistical analysis processing is requested to a host computer. When update information of the fraud parameter used for the judgment is transmitted together with the request for approval and the newest fraud parameter created by analyzing the newest transaction trend etc.
    Type: Grant
    Filed: November 28, 2007
    Date of Patent: January 31, 2012
    Assignee: Intelligent Wave, Inc.
    Inventors: Susumu Yoshikawa, Masayuki Ise, Daisuke Sato
  • Publication number: 20110265877
    Abstract: The objectives of the present invention are to enable the manufacturing of an organic thin-film photoelectric conversion element under normal atmosphere, improve the photoelectric conversion efficiency of the element, and enhance its durability. A hole-blocking TiO2 layer is created between the photoelectric conversion layer and the electrode by a wet process. In the manufacturing process, the hole-blocking TiO2 layer is air-dried so that it will be an amorphous layer. It is possible to provide a concentration gradient layer of PCBM/P3HT in which the PCBM concentration is higher in a region close to the hole-blocking TiO2 layer. This structure will reduce the electric resistance of that region and minimize the current loss within the photoelectric conversion element. In the vicinity of the hole-blocking TiO2 layer, the PCBM concentration is increased, which in turn makes it easier for electrons to flow into the TiO2 layer since PCBM is electrically conductive.
    Type: Application
    Filed: April 25, 2011
    Publication date: November 3, 2011
    Applicant: KYOTO UNIVERSITY
    Inventors: Susumu Yoshikawa, Kaku Uehara, Akinobu Hayakawa
  • Patent number: 8044450
    Abstract: A semiconductor device comprising a resistance element with a high resistance and high resistance accuracy and a non-volatile semiconductor storage element is rationally realized by comprising the non-volatile semiconductor storage element comprising a first isolation formed to isolate a first semiconductor area, a first insulator, and a first electrode in a self-aligned manner, and a second electrode, and the resistance element comprising a second isolation formed to isolate a second semiconductor area, a third insulator and a conductor layer in a self-aligned manner, and third and fourth electrodes formed on each end of the conductor layer via a fourth insulator, and connected with the conductor layer. The conductor layer or the third and fourth electrodes include the same material with the first or second electrode, respectively.
    Type: Grant
    Filed: July 6, 2005
    Date of Patent: October 25, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsuhiro Noguchi, Susumu Yoshikawa, Koichi Fukuda
  • Patent number: 8013321
    Abstract: A composite of a base and an array of needle-like crystals formed on the surface of the base is provided, in which the base side and the opposite side to the base with respect to the array can be isolated in a satisfactory manner. A composite 10 includes a transparent electrode 2 serving as the base, an array 4 of needle-like crystals 3 formed thereon, and a coating film 15 covering the surface of the needle-like crystals 3. The needle-like crystals 3 are made of, for example, zinc oxide, and the coating film 15 contains, for example, titanium oxide. The array 4 includes a first region R1 on the transparent electrode 2 side and a second region R2 on the opposite side to the transparent electrode 2 with respect to the first region R1.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: September 6, 2011
    Assignees: Kyocera Corporation, Susumu Yoshikawa
    Inventors: Junji Aranami, Susumu Yoshikawa
  • Patent number: 8012530
    Abstract: The objectives of the present invention are to enable the manufacturing of an organic thin-film photoelectric conversion element under normal atmosphere, improve the photoelectric conversion efficiency of the element, and enhance its durability. A hole-blocking TiO2 layer is created between the photoelectric conversion layer and the electrode by a wet process. In the manufacturing process, the hole-blocking TiO2 layer is air-dried so that it will be an amorphous layer. It is possible to provide a concentration gradient layer of PCBM/P3HT in which the PCBM concentration is higher in a region close to the hole-blocking TiO2 layer. This structure will reduce the electric resistance of that region and minimize the current loss within the photoelectric conversion element. In the vicinity of the hole-blocking TiO2 layer, the PCBM concentration is increased, which in turn makes it easier for electrons to flow into the TiO2 layer since PCBM is electrically conductive.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: September 6, 2011
    Assignee: Kyoto University
    Inventors: Susumu Yoshikawa, Kaku Uehara, Akinobu Hayakawa
  • Publication number: 20100327056
    Abstract: A payment approval system and a method for approving a payment for credit cards are provided for providing efficient processing while maintaining accuracy in detection of fraud usage of credit cards with an IC chip. Fraud parameters obtained by modeling a pattern of fraud usage is stored in the IC chip equipped in the IC credit card to use for payment approval to achieve improved reliability of offline approval. When offline approval process finds a possibility of fraud usage, online approval for more detailed statistical analysis processing is requested to a host computer. When update information of the fraud parameter used for the judgment is transmitted together with the request for approval and the newest fraud parameter created by analyzing the newest transaction trend etc.
    Type: Application
    Filed: November 28, 2007
    Publication date: December 30, 2010
    Inventors: Susumu Yoshikawa, Masayuki Ise, Daisuke Sato
  • Patent number: 7732854
    Abstract: A nonvolatile semiconductor memory includes a first and a second active area configured to extend in the column direction in parallel; an element isolating region configured to electrically separate the first and the second active area; a plurality of word lines configured to extend in the row direction and be constituted by respective main parts and respective ends; and a plurality of memory cell transistors configured to be disposed on intersections between the respective main parts of the plurality of word lines and the second active area. Each memory cell transistor comprises a gate insulating film, a floating gate electrode, an inter-gate insulating film, and a control gate electrode, constituting a memory cell array; a short-circuit region configured to electrically short circuit the ends of the plurality of word lines; and a trench configured to separate the ends from the main parts of the plurality of word lines.
    Type: Grant
    Filed: November 19, 2007
    Date of Patent: June 8, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Susumu Yoshikawa
  • Publication number: 20100043859
    Abstract: A composite of a base and an array of needle-like crystals formed on a surface of the base is provided, in which the base side and the opposite side to the base with respect to the array can be isolated in a satisfactory manner. A composite 10 contains a transparent electrode 2 serving as the base and an array 4 of needle-like crystals 3 formed thereon. The needle-like crystals 3 are made of, for example, zinc oxide. The array 4 includes a first region R1 on the transparent electrode 2 side and a second region R2 on the opposite side to the transparent electrode 2 with respect to the first region R1. A proportion of the cross section of the needle-like crystals 3 in a plane parallel to the surface of the transparent electrode 2 is lower in the second region R2 than in the first region R1, and the surface of the transparent electrode 2 is substantially covered with the needle-like crystals 3 in the first region R1.
    Type: Application
    Filed: May 30, 2006
    Publication date: February 25, 2010
    Applicants: KYOCERA CORPORATION
    Inventors: Junji Aranami, Susumu Yoshikawa
  • Patent number: 7608488
    Abstract: A manufacturing method of a semiconductor memory device for manufacturing a first semiconductor device and a second semiconductor device wherein a cell array ratio is smaller than that of the first semiconductor device, said manufacturing method has forming the height of first element-isolating insulating films of first memory cell array region of said first semiconductor device so as to be a predetermined height, by performing etching treatment under predetermined conditions using a first etching mask having a first opening for exposing the entirety of said first memory cell array region, and forming the height of second element-isolating insulating films of second memory cell array region and part of peripheral circuit region of said second semiconductor device so as to be the predetermined height, by performing etching treatment under said predetermined conditions using a second etching mask having a second opening for exposing the entirety of said second memory cell array region and a third opening for ex
    Type: Grant
    Filed: October 18, 2007
    Date of Patent: October 27, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuyuki Baba, Susumu Yoshikawa
  • Publication number: 20090151787
    Abstract: The objectives of the present invention are to enable the manufacturing of an organic thin-film photoelectric conversion element under normal atmosphere, improve the photoelectric conversion efficiency of the element, and enhance its durability. A hole-blocking TiO2 layer is created between the photoelectric conversion layer and the electrode by a wet process. In the manufacturing process, the hole-blocking TiO2 layer is air-dried so that it will be an amorphous layer. It is possible to provide a concentration gradient layer of PCBM/P3HT in which the PCBM concentration is higher in a region close to the hole-blocking TiO2 layer. This structure will reduce the electric resistance of that region and minimize the current loss within the photoelectric conversion element. In the vicinity of the hole-blocking TiO2 layer, the PCBM concentration is increased, which in turn makes it easier for electrons to flow into the TiO2 layer since PCBM is electrically conductive.
    Type: Application
    Filed: September 6, 2006
    Publication date: June 18, 2009
    Applicant: KYOTO UNIVERSITY
    Inventors: Susumu Yoshikawa, Kaku Uehara, Akinobu Hayakawa
  • Publication number: 20080258201
    Abstract: A manufacturing method of a semiconductor memory device for manufacturing a first semiconductor device and a second semiconductor device wherein a cell array ratio is smaller than that of the first semiconductor device, said manufacturing method has forming the height of first element-isolating insulating films of first memory cell array region of said first semiconductor device so as to be a predetermined height, by performing etching treatment under predetermined conditions using a first etching mask having a first opening for exposing the entirety of said first memory cell array region, and forming the height of second element-isolating insulating films of second memory cell array region and part of peripheral circuit region of said second semiconductor device so as to be the predetermined height, by performing etching treatment under said predetermined conditions using a second etching mask having a second opening for exposing the entirety of said second memory cell array region and a third opening for ex
    Type: Application
    Filed: October 18, 2007
    Publication date: October 23, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yasuyuki BABA, Susumu Yoshikawa
  • Publication number: 20080074926
    Abstract: A nonvolatile semiconductor memory includes a first and a second active area configured to extend in the column direction in parallel; an element isolating region configured to electrically separate the first and the second active area; a plurality of word lines configured to extend in the row direction and be constituted by respective main parts and respective ends; and a plurality of memory cell transistors configured to be disposed on intersections between the respective main parts of the plurality of word lines and the second active area. Each memory cell transistor comprises a gate insulating film, a floating gate electrode, an inter-gate insulating film, and a control gate electrode, constituting a memory cell array; a short-circuit region configured to electrically short circuit the ends of the plurality of word lines; and a trench configured to separate the ends from the main parts of the plurality of word lines.
    Type: Application
    Filed: November 19, 2007
    Publication date: March 27, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Susumu Yoshikawa